Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: bypass querying ras error count registers
Once ras recovery is issued by ras sync flood interrupt or
ras controller interrupt, add this guard to bypass or execute
ras error count register harvest of all IPs.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Guchun Chen
and committed by
Alex Deucher
f75e94d8
0cf0ee98
+38
-29
+12
-10
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+12
-10
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
···
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struct list_head device_list, *device_list_handle = NULL;
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struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);
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-
/* Build list of devices to query RAS related errors */
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-
if (hive && adev->gmc.xgmi.num_physical_nodes > 1)
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-
device_list_handle = &hive->device_list;
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-
else {
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INIT_LIST_HEAD(&device_list);
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list_add_tail(&adev->gmc.xgmi.head, &device_list);
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-
device_list_handle = &device_list;
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-
}
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+
if (!ras->disable_ras_err_cnt_harvest) {
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+
/* Build list of devices to query RAS related errors */
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+
if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
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+
device_list_handle = &hive->device_list;
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+
} else {
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+
INIT_LIST_HEAD(&device_list);
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+
list_add_tail(&adev->gmc.xgmi.head, &device_list);
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+
device_list_handle = &device_list;
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+
}
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-
list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) {
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-
amdgpu_ras_log_on_err_counter(remote_adev);
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+
list_for_each_entry(remote_adev,
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+
device_list_handle, gmc.xgmi.head)
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+
amdgpu_ras_log_on_err_counter(remote_adev);
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}
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if (amdgpu_device_should_recover_gpu(ras->adev))
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
+23
-19
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+23
-19
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
···
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uint32_t bif_doorbell_intr_cntl;
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
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struct ras_err_data err_data = {0, 0, 0, NULL};
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+
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
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if (REG_GET_FIELD(bif_doorbell_intr_cntl,
···
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RAS_CNTLR_INTERRUPT_CLEAR, 1);
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WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
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-
/*
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* clear error status after ras_controller_intr according to
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-
* hw team and count ue number for query
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-
*/
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-
nbio_v7_4_query_ras_error_count(adev, &err_data);
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+
if (!ras->disable_ras_err_cnt_harvest) {
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+
/*
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+
* clear error status after ras_controller_intr
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+
* according to hw team and count ue number
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+
* for query
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+
*/
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+
nbio_v7_4_query_ras_error_count(adev, &err_data);
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-
/* logging on error counter and printing for awareness */
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-
obj->err_data.ue_count += err_data.ue_count;
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-
obj->err_data.ce_count += err_data.ce_count;
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+
/* logging on error cnt and printing for awareness */
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+
obj->err_data.ue_count += err_data.ue_count;
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+
obj->err_data.ce_count += err_data.ce_count;
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-
if (err_data.ce_count)
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-
dev_info(adev->dev, "%ld correctable hardware "
328
-
"errors detected in %s block, "
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-
"no user action is needed.\n",
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-
obj->err_data.ce_count,
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-
adev->nbio.ras_if->name);
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+
if (err_data.ce_count)
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+
dev_info(adev->dev, "%ld correctable hardware "
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+
"errors detected in %s block, "
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+
"no user action is needed.\n",
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+
obj->err_data.ce_count,
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+
adev->nbio.ras_if->name);
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-
if (err_data.ue_count)
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-
dev_info(adev->dev, "%ld uncorrectable hardware "
335
-
"errors detected in %s block\n",
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-
obj->err_data.ue_count,
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-
adev->nbio.ras_if->name);
334
+
if (err_data.ue_count)
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+
dev_info(adev->dev, "%ld uncorrectable hardware "
336
+
"errors detected in %s block\n",
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+
obj->err_data.ue_count,
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+
adev->nbio.ras_if->name);
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+
}
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dev_info(adev->dev, "RAS controller interrupt triggered "
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"by NBIF error\n");