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phy/rockchip: inno-hdmi: force set_rate on power_on

Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and
not in pixel clock rate.
When the hdmiphy clock is configured with the same pixel clock rate using
clk_set_rate() the clock framework do not signal the hdmi phy driver
to set_rate when switching between 8-bit and Deep Color.
This result in pre/post pll not being re-configured when switching between
regular 8-bit and Deep Color video formats.

Fix this by calling set_rate in power_on to force pre pll re-configuration.

Signed-off-by: Huicong Xu <xhc@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-6-jonas@kwiboo.se
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Huicong Xu and committed by
Vinod Koul f79b812b 19a1d46b

+13
+13
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
··· 245 245 struct clk_hw hw; 246 246 struct clk *phyclk; 247 247 unsigned long pixclock; 248 + unsigned long tmdsclock; 248 249 }; 249 250 250 251 struct pre_pll_config { ··· 486 485 487 486 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); 488 487 488 + inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); 489 + 489 490 ret = clk_prepare_enable(inno->phyclk); 490 491 if (ret) 491 492 return ret; ··· 511 508 inno->plat_data->ops->power_off(inno); 512 509 513 510 clk_disable_unprepare(inno->phyclk); 511 + 512 + inno->tmdsclock = 0; 514 513 515 514 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); 516 515 ··· 633 628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", 634 629 __func__, rate, tmdsclock); 635 630 631 + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) 632 + return 0; 633 + 636 634 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); 637 635 if (IS_ERR(cfg)) 638 636 return PTR_ERR(cfg); ··· 678 670 } 679 671 680 672 inno->pixclock = rate; 673 + inno->tmdsclock = tmdsclock; 681 674 682 675 return 0; 683 676 } ··· 790 781 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", 791 782 __func__, rate, tmdsclock); 792 783 784 + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) 785 + return 0; 786 + 793 787 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); 794 788 if (IS_ERR(cfg)) 795 789 return PTR_ERR(cfg); ··· 832 820 } 833 821 834 822 inno->pixclock = rate; 823 + inno->tmdsclock = tmdsclock; 835 824 836 825 return 0; 837 826 }