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usb: dwc2: New bitfield definition and programming in GRSTCTL

Added new bitfield GRSTCTL_CLOCK_SWITH_TIMER in GRSTCTL register.
This bitfield applicable HSOTG cores v5.00 or higher and not
applicable to HS/FS IOT devices.
This bitfield must be programmed to 3'b010 if core will be
used in Low-speed and core configured for any HS/FS PHY interface.
This bitfield must be programmed to 3'b111 if core configured
to use either:
- HS PHY interface UTMI or ULPI
- FS PHY any interface

Signed-off-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
Link: https://lore.kernel.org/r/0616838cfee958774c9321c6eeeda4be92f900d8.1708948356.git.Minas.Harutyunyan@synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Minas Harutyunyan and committed by
Greg Kroah-Hartman f8453bbd 4483ef3c

+48
+37
drivers/usb/dwc2/core.c
··· 980 980 dwc2_writel(hsotg, hcfg, HCFG); 981 981 } 982 982 983 + static void dwc2_set_clock_switch_timer(struct dwc2_hsotg *hsotg) 984 + { 985 + u32 grstctl, gsnpsid, val = 0; 986 + 987 + gsnpsid = dwc2_readl(hsotg, GSNPSID); 988 + 989 + /* 990 + * Applicable only to HSOTG core v5.00a or higher. 991 + * Not applicable to HS/FS IOT devices. 992 + */ 993 + if ((gsnpsid & ~DWC2_CORE_REV_MASK) != DWC2_OTG_ID || 994 + gsnpsid < DWC2_CORE_REV_5_00a) 995 + return; 996 + 997 + if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI && 998 + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || 999 + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 1000 + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) || 1001 + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && 1002 + hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED)) { 1003 + val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS; 1004 + } 1005 + 1006 + if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW && 1007 + hsotg->hw_params.hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED && 1008 + hsotg->hw_params.fs_phy_type != GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED) { 1009 + val = GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147; 1010 + } 1011 + 1012 + grstctl = dwc2_readl(hsotg, GRSTCTL); 1013 + grstctl &= ~GRSTCTL_CLOCK_SWITH_TIMER_MASK; 1014 + grstctl |= GRSTCTL_CLOCK_SWITH_TIMER(val); 1015 + dwc2_writel(hsotg, grstctl, GRSTCTL); 1016 + } 1017 + 983 1018 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 984 1019 { 985 1020 u32 usbcfg, ggpio, i2cctl; ··· 1031 996 if (!(usbcfg & GUSBCFG_PHYSEL)) { 1032 997 usbcfg |= GUSBCFG_PHYSEL; 1033 998 dwc2_writel(hsotg, usbcfg, GUSBCFG); 999 + 1000 + dwc2_set_clock_switch_timer(hsotg); 1034 1001 1035 1002 /* Reset after a PHY select */ 1036 1003 retval = dwc2_core_reset(hsotg, false);
+11
drivers/usb/dwc2/hw.h
··· 99 99 #define GRSTCTL_AHBIDLE BIT(31) 100 100 #define GRSTCTL_DMAREQ BIT(30) 101 101 #define GRSTCTL_CSFTRST_DONE BIT(29) 102 + #define GRSTCTL_CLOCK_SWITH_TIMER_MASK (0x7 << 11) 103 + #define GRSTCTL_CLOCK_SWITH_TIMER_SHIFT 11 104 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_19 0x0 105 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_15 0x1 106 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_147 0x2 107 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_50 0x3 108 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_100 0x4 109 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_125 0x5 110 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_200 0x6 111 + #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_DIS 0x7 112 + #define GRSTCTL_CLOCK_SWITH_TIMER(_x) ((_x) << 11) 102 113 #define GRSTCTL_TXFNUM_MASK (0x1f << 6) 103 114 #define GRSTCTL_TXFNUM_SHIFT 6 104 115 #define GRSTCTL_TXFNUM_LIMIT 0x1f