Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: move CNP clock gating init into intel_pch
Move the CNP PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding
CFL/CML caller to the display-specific code.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-5-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+11
-12
+10
drivers/gpu/drm/i915/display/intel_pch.c
+10
drivers/gpu/drm/i915/display/intel_pch.c
···
279
279
TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
280
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}
281
281
282
+
static void intel_pch_cnp_init_clock_gating(struct intel_display *display)
283
+
{
284
+
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
285
+
intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
286
+
CNP_PWM_CGE_GATING_DISABLE);
287
+
}
288
+
282
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void intel_pch_init_clock_gating(struct intel_display *display)
283
290
{
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switch (INTEL_PCH_TYPE(display)) {
···
298
291
case PCH_LPT_H:
299
292
case PCH_LPT_LP:
300
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intel_pch_lpt_init_clock_gating(display);
294
+
break;
295
+
case PCH_CNP:
296
+
intel_pch_cnp_init_clock_gating(display);
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break;
302
298
default:
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299
break;
+1
-12
drivers/gpu/drm/i915/intel_clock_gating.c
+1
-12
drivers/gpu/drm/i915/intel_clock_gating.c
···
299
299
SGSI_SIDECLK_DIS);
300
300
}
301
301
302
-
static void cnp_init_clock_gating(struct drm_i915_private *i915)
303
-
{
304
-
struct intel_display *display = i915->display;
305
-
306
-
if (!HAS_PCH_CNP(display))
307
-
return;
308
-
309
-
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
310
-
intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
311
-
}
312
-
313
302
static void cfl_init_clock_gating(struct drm_i915_private *i915)
314
303
{
315
-
cnp_init_clock_gating(i915);
304
+
intel_pch_init_clock_gating(i915->display);
316
305
gen9_init_clock_gating(i915);
317
306
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307
/* WAC6entrylatency:cfl */