Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-5.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC fixes from Vineet Gupta:
- hsdk platform unifying apertures
- build system CROSS_COMPILE prefix
* tag 'arc-5.2-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: [plat-hsdk]: unify memory apertures configuration
ARC: build: Try to guess CROSS_COMPILE with cc-cross-prefix
+157
-8
+4
arch/arc/Makefile
+4
arch/arc/Makefile
···
5
5
6
6
KBUILD_DEFCONFIG := nsim_hs_defconfig
7
7
8
+
ifeq ($(CROSS_COMPILE),)
9
+
CROSS_COMPILE := $(call cc-cross-prefix, arc-linux- arceb-linux-)
10
+
endif
11
+
8
12
cflags-y += -fno-common -pipe -fno-builtin -mmedium-calls -D__linux__
9
13
cflags-$(CONFIG_ISA_ARCOMPACT) += -mA7
10
14
cflags-$(CONFIG_ISA_ARCV2) += -mcpu=hs38
+153
-8
arch/arc/plat-hsdk/platform.c
+153
-8
arch/arc/plat-hsdk/platform.c
···
32
32
33
33
#define ARC_PERIPHERAL_BASE 0xf0000000
34
34
#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
35
-
#define CREG_PAE (CREG_BASE + 0x180)
36
-
#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
37
35
38
36
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
39
37
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
···
97
99
iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
98
100
}
99
101
100
-
static void __init hsdk_init_early(void)
102
+
enum hsdk_axi_masters {
103
+
M_HS_CORE = 0,
104
+
M_HS_RTT,
105
+
M_AXI_TUN,
106
+
M_HDMI_VIDEO,
107
+
M_HDMI_AUDIO,
108
+
M_USB_HOST,
109
+
M_ETHERNET,
110
+
M_SDIO,
111
+
M_GPU,
112
+
M_DMAC_0,
113
+
M_DMAC_1,
114
+
M_DVFS
115
+
};
116
+
117
+
#define UPDATE_VAL 1
118
+
119
+
/*
120
+
* This is modified configuration of AXI bridge. Default settings
121
+
* are specified in "Table 111 CREG Address Decoder register reset values".
122
+
*
123
+
* AXI_M_m_SLV{0|1} - Slave Select register for master 'm'.
124
+
* Possible slaves are:
125
+
* - 0 => no slave selected
126
+
* - 1 => DDR controller port #1
127
+
* - 2 => SRAM controller
128
+
* - 3 => AXI tunnel
129
+
* - 4 => EBI controller
130
+
* - 5 => ROM controller
131
+
* - 6 => AXI2APB bridge
132
+
* - 7 => DDR controller port #2
133
+
* - 8 => DDR controller port #3
134
+
* - 9 => HS38x4 IOC
135
+
* - 10 => HS38x4 DMI
136
+
* AXI_M_m_OFFSET{0|1} - Addr Offset register for master 'm'
137
+
*
138
+
* Please read ARC HS Development IC Specification, section 17.2 for more
139
+
* information about apertures configuration.
140
+
*
141
+
* m master AXI_M_m_SLV0 AXI_M_m_SLV1 AXI_M_m_OFFSET0 AXI_M_m_OFFSET1
142
+
* 0 HS (CBU) 0x11111111 0x63111111 0xFEDCBA98 0x0E543210
143
+
* 1 HS (RTT) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
144
+
* 2 AXI Tunnel 0x88888888 0x88888888 0xFEDCBA98 0x76543210
145
+
* 3 HDMI-VIDEO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
146
+
* 4 HDMI-ADUIO 0x77777777 0x77777777 0xFEDCBA98 0x76543210
147
+
* 5 USB-HOST 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
148
+
* 6 ETHERNET 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
149
+
* 7 SDIO 0x77777777 0x77999999 0xFEDCBA98 0x76DCBA98
150
+
* 8 GPU 0x77777777 0x77777777 0xFEDCBA98 0x76543210
151
+
* 9 DMAC (port #1) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
152
+
* 10 DMAC (port #2) 0x77777777 0x77777777 0xFEDCBA98 0x76543210
153
+
* 11 DVFS 0x00000000 0x60000000 0x00000000 0x00000000
154
+
*/
155
+
156
+
#define CREG_AXI_M_SLV0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m)))
157
+
#define CREG_AXI_M_SLV1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))
158
+
#define CREG_AXI_M_OFT0(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))
159
+
#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
160
+
#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
161
+
162
+
#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
163
+
164
+
#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
165
+
#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
166
+
167
+
static void __init hsdk_init_memory_bridge(void)
101
168
{
169
+
u32 reg;
170
+
171
+
/*
172
+
* M_HS_CORE has one unique register - BOOT.
173
+
* We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
174
+
* aperture to be masked by 'boot mirror'.
175
+
*/
176
+
reg = readl(CREG_AXI_M_HS_CORE_BOOT) & (~0x3);
177
+
writel(reg, CREG_AXI_M_HS_CORE_BOOT);
178
+
writel(0x11111111, CREG_AXI_M_SLV0(M_HS_CORE));
179
+
writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));
180
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));
181
+
writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
182
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
183
+
184
+
writel(0x77777777, CREG_AXI_M_SLV0(M_HS_RTT));
185
+
writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));
186
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));
187
+
writel(0x76543210, CREG_AXI_M_OFT1(M_HS_RTT));
188
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_RTT));
189
+
190
+
writel(0x88888888, CREG_AXI_M_SLV0(M_AXI_TUN));
191
+
writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));
192
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));
193
+
writel(0x76543210, CREG_AXI_M_OFT1(M_AXI_TUN));
194
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_AXI_TUN));
195
+
196
+
writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_VIDEO));
197
+
writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));
198
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));
199
+
writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_VIDEO));
200
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_VIDEO));
201
+
202
+
writel(0x77777777, CREG_AXI_M_SLV0(M_HDMI_AUDIO));
203
+
writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));
204
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));
205
+
writel(0x76543210, CREG_AXI_M_OFT1(M_HDMI_AUDIO));
206
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HDMI_AUDIO));
207
+
208
+
writel(0x77777777, CREG_AXI_M_SLV0(M_USB_HOST));
209
+
writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));
210
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));
211
+
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_USB_HOST));
212
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
213
+
214
+
writel(0x77777777, CREG_AXI_M_SLV0(M_ETHERNET));
215
+
writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));
216
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));
217
+
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_ETHERNET));
218
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
219
+
220
+
writel(0x77777777, CREG_AXI_M_SLV0(M_SDIO));
221
+
writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));
222
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));
223
+
writel(0x76DCBA98, CREG_AXI_M_OFT1(M_SDIO));
224
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
225
+
226
+
writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
227
+
writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
228
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
229
+
writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
230
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
231
+
232
+
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
233
+
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
234
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
235
+
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
236
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
237
+
238
+
writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
239
+
writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
240
+
writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
241
+
writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
242
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
243
+
244
+
writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
245
+
writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
246
+
writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
247
+
writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
248
+
writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
249
+
102
250
/*
103
251
* PAE remapping for DMA clients does not work due to an RTL bug, so
104
252
* CREG_PAE register must be programmed to all zeroes, otherwise it
105
253
* will cause problems with DMA to/from peripherals even if PAE40 is
106
254
* not used.
107
255
*/
256
+
writel(0x00000000, CREG_PAE);
257
+
writel(UPDATE_VAL, CREG_PAE_UPDT);
258
+
}
108
259
109
-
/* Default is 1, which means "PAE offset = 4GByte" */
110
-
writel_relaxed(0, (void __iomem *) CREG_PAE);
111
-
112
-
/* Really apply settings made above */
113
-
writel(1, (void __iomem *) CREG_PAE_UPDATE);
260
+
static void __init hsdk_init_early(void)
261
+
{
262
+
hsdk_init_memory_bridge();
114
263
115
264
/*
116
265
* Switch SDIO external ciu clock divider from default div-by-8 to