Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Perform basic checks on pin config properties so as not to allow
directly contradictory settings such as setting a pin to more than
one bias or drive mode
- Handle input-threshold-voltage-microvolt property
- Introduce pinctrl_gpio_get_config() handling in the core for SCMI
GPIO using pin control
New drivers:
- GPIO-by-pin control driver (also appearing in the GPIO pull
request) fulfilling a promise on a comment from Grant Likely many
years ago: "can't GPIO just be a front-end for pin control?" it
turns out it can, if and only if you design something new from
scratch, such as SCMI
- Broadcom BCM7038 as a pinctrl-single delegate
- Mobileye EyeQ6Lplus OLB pin controller
- Qualcomm Eliza and Hawi families TLMM pin controllers
- Qualcomm SDM670 and Milos family LPASS LPI pin controllers
- Qualcomm IPQ5210 pin controller
- Realtek RTD1625 pin controller support
- Rockchip RV1103B pin controller support
- Texas Instruments AM62L as a pinctrl-single delegate
Improvements:
- Set config implementation for the Spacemit K1 pin controller"
* tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits)
pinctrl: qcom: Add Hawi pinctrl driver
dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
pinctrl: single: Add bcm7038-padconf compatible matching
dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
pinctrl: qcom: sdm670-lpass-lpi: label variables as static
pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description
pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description
pinctrl: qcom: add sdm670 lpi tlmm
dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
pinctrl: qcom: Introduce IPQ5210 TLMM driver
dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs
pinctrl: qcom: eliza: Fix interrupt target bit
pinctrl: core: Don't use "proxy" headers
pinctrl: amd: Support new ACPI ID AMDI0033
pinctrl: renesas: rzg2l: Drop superfluous blank line
pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers
...
+9879
-606
+3
-1
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
+3
-1
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
+126
Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml
+126
Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller
8
+
9
+
maintainers:
10
+
- Frank Li <Frank.Li@nxp.com>
11
+
12
+
description:
13
+
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14
+
for common binding part and usage.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- fsl,imx1-iomuxc
20
+
- fsl,imx27-iomuxc
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
'#address-cells':
26
+
const: 1
27
+
28
+
'#size-cells':
29
+
const: 1
30
+
31
+
ranges: true
32
+
33
+
patternProperties:
34
+
'^gpio@[0-9a-f]+$':
35
+
type: object
36
+
$ref: /schemas/gpio/fsl-imx-gpio.yaml
37
+
unevaluatedProperties: false
38
+
39
+
'grp$':
40
+
type: object
41
+
description:
42
+
Pinctrl node's client devices use subnodes for desired pin configuration.
43
+
Client device subnodes use below standard properties.
44
+
45
+
properties:
46
+
fsl,pins:
47
+
description:
48
+
three integers array, represents a group of pins mux and config
49
+
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
50
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
51
+
items:
52
+
items:
53
+
- description:
54
+
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32
55
+
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN
56
+
is the pin number on the specific port (between 0 and 31)
57
+
- description: |
58
+
MUX_ID is function + (direction << 2) + (gpio_oconf << 4)
59
+
+ (gpio_iconfa << 8) + (gpio_iconfb << 10)
60
+
61
+
function value is used to select the pin function.
62
+
Possible values:
63
+
0 - Primary function
64
+
1 - Alternate function
65
+
2 - GPIO
66
+
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
67
+
68
+
direction defines the data direction of the pin.
69
+
Possible values:
70
+
0 - Input
71
+
1 - Output
72
+
Register: DDIR
73
+
74
+
gpio_oconf configures the gpio submodule output signal.
75
+
This does not have any effect unless GPIO function is
76
+
selected. A/B/C_IN are output signals of function blocks
77
+
A,B and C. Specific function blocks are described in the
78
+
reference manual.
79
+
Possible values:
80
+
0 - A_IN
81
+
1 - B_IN
82
+
2 - C_IN
83
+
3 - Data Register
84
+
Registers: OCR1, OCR2
85
+
86
+
gpio_iconfa/b configures the gpio submodule input to
87
+
functionblocks A and B. GPIO function should be selected if
88
+
this is configured.
89
+
Possible values:
90
+
0 - GPIO_IN
91
+
1 - Interrupt Status Register
92
+
2 - Pulldown
93
+
3 - Pullup
94
+
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
95
+
96
+
- description:
97
+
CONFIG can be 0 or 1, meaning Pullup disable/enable.
98
+
required:
99
+
- fsl,pins
100
+
101
+
additionalProperties: false
102
+
103
+
required:
104
+
- compatible
105
+
- reg
106
+
107
+
allOf:
108
+
- $ref: pinctrl.yaml#
109
+
110
+
unevaluatedProperties: false
111
+
112
+
examples:
113
+
- |
114
+
pinmux@10015000 {
115
+
compatible = "fsl,imx27-iomuxc";
116
+
reg = <0x10015000 0x600>;
117
+
118
+
uartgrp {
119
+
fsl,pins = <
120
+
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
121
+
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
122
+
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
123
+
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
124
+
>;
125
+
};
126
+
};
-121
Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
-121
Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
···
1
-
* Freescale IMX27 IOMUX Controller
2
-
3
-
Required properties:
4
-
- compatible: "fsl,imx27-iomuxc"
5
-
6
-
The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
7
-
8
-
Required properties for pin configuration node:
9
-
- fsl,pins: three integers array, represents a group of pins mux and config
10
-
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
11
-
12
-
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
13
-
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
14
-
number on the specific port (between 0 and 31).
15
-
16
-
MUX_ID is
17
-
function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
18
-
19
-
function value is used to select the pin function.
20
-
Possible values:
21
-
0 - Primary function
22
-
1 - Alternate function
23
-
2 - GPIO
24
-
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
25
-
26
-
direction defines the data direction of the pin.
27
-
Possible values:
28
-
0 - Input
29
-
1 - Output
30
-
Register: DDIR
31
-
32
-
gpio_oconf configures the gpio submodule output signal. This does not
33
-
have any effect unless GPIO function is selected. A/B/C_IN are output
34
-
signals of function blocks A,B and C. Specific function blocks are
35
-
described in the reference manual.
36
-
Possible values:
37
-
0 - A_IN
38
-
1 - B_IN
39
-
2 - C_IN
40
-
3 - Data Register
41
-
Registers: OCR1, OCR2
42
-
43
-
gpio_iconfa/b configures the gpio submodule input to functionblocks A and
44
-
B. GPIO function should be selected if this is configured.
45
-
Possible values:
46
-
0 - GPIO_IN
47
-
1 - Interrupt Status Register
48
-
2 - Pulldown
49
-
3 - Pullup
50
-
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
51
-
52
-
CONFIG can be 0 or 1, meaning Pullup disable/enable.
53
-
54
-
55
-
The iomux controller has gpio child nodes which are embedded in the iomux
56
-
control registers. They have to be defined as child nodes of the iomux device
57
-
node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
58
-
properties for the iomux device node are required.
59
-
60
-
Example:
61
-
62
-
iomuxc: iomuxc@10015000 {
63
-
compatible = "fsl,imx27-iomuxc";
64
-
reg = <0x10015000 0x600>;
65
-
#address-cells = <1>;
66
-
#size-cells = <1>;
67
-
ranges;
68
-
69
-
gpio1: gpio@10015000 {
70
-
...
71
-
};
72
-
73
-
...
74
-
75
-
uart {
76
-
pinctrl_uart1: uart-1 {
77
-
fsl,pins = <
78
-
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
79
-
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
80
-
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
81
-
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
82
-
>;
83
-
};
84
-
85
-
...
86
-
};
87
-
};
88
-
89
-
90
-
For convenience there are macros defined in imx27-pinfunc.h which provide PIN
91
-
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
92
-
are defined in the i.MX27 reference manual.
93
-
94
-
The above example using macros:
95
-
96
-
iomuxc: iomuxc@10015000 {
97
-
compatible = "fsl,imx27-iomuxc";
98
-
reg = <0x10015000 0x600>;
99
-
#address-cells = <1>;
100
-
#size-cells = <1>;
101
-
ranges;
102
-
103
-
gpio1: gpio@10015000 {
104
-
...
105
-
};
106
-
107
-
...
108
-
109
-
uart {
110
-
pinctrl_uart1: uart-1 {
111
-
fsl,pins = <
112
-
MX27_PAD_UART1_TXD__UART1_TXD 0x0
113
-
MX27_PAD_UART1_RXD__UART1_RXD 0x0
114
-
MX27_PAD_UART1_CTS__UART1_CTS 0x0
115
-
MX27_PAD_UART1_RTS__UART1_RTS 0x0
116
-
>;
117
-
};
118
-
119
-
...
120
-
};
121
-
};
+1
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
+6
-5
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
+6
-5
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
···
84
84
85
85
properties:
86
86
groups:
87
-
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
88
-
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
89
-
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
90
-
spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
91
-
usb2_drvvbus1, usb32_drvvbus0 ]
87
+
items:
88
+
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
89
+
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
90
+
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb,
91
+
smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
92
+
usb2_drvvbus1, usb32_drvvbus0 ]
92
93
93
94
function:
94
95
enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
+98
Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml
+98
Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Pinmux controller function for Maxim MAX77620 Power management IC
8
+
9
+
maintainers:
10
+
- Svyatoslav Ryhel <clamor95@gmail.com>
11
+
12
+
description:
13
+
Device has 8 GPIO pins which can be configured as GPIO as well as the
14
+
special IO functions.
15
+
16
+
allOf:
17
+
- $ref: /schemas/pinctrl/pincfg-node.yaml
18
+
- $ref: /schemas/pinctrl/pinmux-node.yaml
19
+
20
+
patternProperties:
21
+
"^(pin|gpio).":
22
+
type: object
23
+
additionalProperties: false
24
+
25
+
properties:
26
+
pins:
27
+
items:
28
+
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ]
29
+
30
+
function:
31
+
items:
32
+
enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in,
33
+
reference-out ]
34
+
35
+
drive-push-pull: true
36
+
drive-open-drain: true
37
+
bias-pull-up: true
38
+
bias-pull-down: true
39
+
40
+
maxim,active-fps-source:
41
+
$ref: /schemas/types.yaml#/definitions/uint32
42
+
description: |
43
+
FPS source for the GPIOs to get enabled/disabled when system is in
44
+
active state. Valid values are:
45
+
- MAX77620_FPS_SRC_0: FPS source is FPS0.
46
+
- MAX77620_FPS_SRC_1: FPS source is FPS1
47
+
- MAX77620_FPS_SRC_2: FPS source is FPS2
48
+
- MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and
49
+
it gets enabled/disabled by register access.
50
+
Absence of this property will leave the FPS configuration register
51
+
for that GPIO to default configuration.
52
+
53
+
maxim,active-fps-power-up-slot:
54
+
$ref: /schemas/types.yaml#/definitions/uint32
55
+
description:
56
+
Sequencing event slot number on which the GPIO get enabled when
57
+
master FPS input event set to HIGH. This is applicable if FPS source
58
+
is selected as FPS0, FPS1 or FPS2.
59
+
enum: [0, 1, 2, 3, 4, 5, 6, 7]
60
+
61
+
maxim,active-fps-power-down-slot:
62
+
$ref: /schemas/types.yaml#/definitions/uint32
63
+
description:
64
+
Sequencing event slot number on which the GPIO get disabled when
65
+
master FPS input event set to LOW. This is applicable if FPS source
66
+
is selected as FPS0, FPS1 or FPS2.
67
+
enum: [0, 1, 2, 3, 4, 5, 6, 7]
68
+
69
+
maxim,suspend-fps-source:
70
+
$ref: /schemas/types.yaml#/definitions/uint32
71
+
description:
72
+
This is same as property "maxim,active-fps-source" but value get
73
+
configured when system enters in to suspend state.
74
+
75
+
maxim,suspend-fps-power-up-slot:
76
+
$ref: /schemas/types.yaml#/definitions/uint32
77
+
description:
78
+
This is same as property "maxim,active-fps-power-up-slot" but this
79
+
value get configured into FPS configuration register when system
80
+
enters into suspend. This is applicable if suspend state FPS source
81
+
is selected as FPS0, FPS1 or FPS2.
82
+
enum: [0, 1, 2, 3, 4, 5, 6, 7]
83
+
84
+
maxim,suspend-fps-power-down-slot:
85
+
$ref: /schemas/types.yaml#/definitions/uint32
86
+
description:
87
+
This is same as property "maxim,active-fps-power-down-slot" but this
88
+
value get configured into FPS configuration register when system
89
+
enters into suspend. This is applicable if suspend state FPS source
90
+
is selected as FPS0, FPS1 or FPS2.
91
+
enum: [0, 1, 2, 3, 4, 5, 6, 7]
92
+
93
+
required:
94
+
- pins
95
+
96
+
additionalProperties: false
97
+
98
+
# see maxim,max77620.yaml for an example
+100
-7
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+100
-7
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
···
162
162
this affects the expected delay in ps before latching a value to
163
163
an output pin.
164
164
165
-
if:
166
-
required:
167
-
- skew-delay
168
-
then:
169
-
properties:
170
-
skew-delay-input-ps: false
171
-
skew-delay-output-ps: false
165
+
input-threshold-voltage-microvolt:
166
+
description: Specifies the input voltage level of the pin in microvolts.
167
+
This defines the reference for VIH (Input High Voltage) and VIL
168
+
(Input Low Voltage) thresholds for proper signal detection.
169
+
170
+
allOf:
171
+
- if:
172
+
required:
173
+
- skew-delay
174
+
then:
175
+
properties:
176
+
skew-delay-input-ps: false
177
+
skew-delay-output-ps: false
178
+
179
+
- if:
180
+
required:
181
+
- input-disable
182
+
then:
183
+
properties:
184
+
input-enable: false
185
+
input-threshold-voltage-microvolt: false
186
+
187
+
- if:
188
+
required:
189
+
- output-disable
190
+
then:
191
+
properties:
192
+
output-enable: false
193
+
output-impedance-ohms: false
194
+
195
+
- if:
196
+
required:
197
+
- output-low
198
+
then:
199
+
properties:
200
+
output-high: false
201
+
202
+
- if:
203
+
required:
204
+
- low-power-enable
205
+
then:
206
+
properties:
207
+
low-power-disable: false
208
+
209
+
- if:
210
+
required:
211
+
- input-schmitt-disable
212
+
then:
213
+
properties:
214
+
input-schmitt-enable: false
215
+
input-schmitt-microvolt: false
216
+
217
+
- if:
218
+
required:
219
+
- drive-strength
220
+
then:
221
+
properties:
222
+
drive-strength-microamp: false
223
+
224
+
- if:
225
+
anyOf:
226
+
- required:
227
+
- drive-open-source
228
+
- required:
229
+
- drive-open-drain
230
+
- required:
231
+
- drive-push-pull
232
+
then:
233
+
oneOf:
234
+
- required:
235
+
- drive-open-source
236
+
- required:
237
+
- drive-open-drain
238
+
- required:
239
+
- drive-push-pull
240
+
241
+
- if:
242
+
anyOf:
243
+
- required:
244
+
- bias-disable
245
+
- required:
246
+
- bias-bus-hold
247
+
- required:
248
+
- bias-pull-up
249
+
- required:
250
+
- bias-pull-down
251
+
- required:
252
+
- bias-pull-pin-default
253
+
then:
254
+
oneOf:
255
+
- required:
256
+
- bias-disable
257
+
- required:
258
+
- bias-bus-hold
259
+
- required:
260
+
- bias-pull-up
261
+
- required:
262
+
- bias-pull-down
263
+
- required:
264
+
- bias-pull-pin-default
172
265
173
266
additionalProperties: true
-127
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
-127
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
···
1
-
Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
2
-
3
-
Device has 8 GPIO pins which can be configured as GPIO as well as the
4
-
special IO functions.
5
-
6
-
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
7
-
for details of the common pinctrl bindings used by client devices,
8
-
including the meaning of the phrase "pin configuration node".
9
-
10
-
Optional Pinmux properties:
11
-
--------------------------
12
-
Following properties are required if default setting of pins are required
13
-
at boot.
14
-
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
15
-
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
16
-
<pinctrl-bindings.txt>.
17
-
18
-
The pin configurations are defined as child of the pinctrl states node. Each
19
-
sub-node have following properties:
20
-
21
-
Required properties:
22
-
------------------
23
-
- pins: List of pins. Valid values of pins properties are:
24
-
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
25
-
26
-
Optional properties:
27
-
-------------------
28
-
Following are optional properties defined as pinmux DT binding document
29
-
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
30
-
on default.
31
-
function,
32
-
drive-push-pull,
33
-
drive-open-drain,
34
-
bias-pull-up,
35
-
bias-pull-down.
36
-
37
-
Valid values for function properties are:
38
-
gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
39
-
reference-out
40
-
41
-
There are also customised properties for the GPIO1, GPIO2 and GPIO3. These
42
-
customised properties are required to configure FPS configuration parameters
43
-
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
44
-
detail of Flexible Power Sequence (FPS).
45
-
46
-
- maxim,active-fps-source: FPS source for the GPIOs to get
47
-
enabled/disabled when system is in
48
-
active state. Valid values are:
49
-
- MAX77620_FPS_SRC_0,
50
-
FPS source is FPS0.
51
-
- MAX77620_FPS_SRC_1,
52
-
FPS source is FPS1
53
-
- MAX77620_FPS_SRC_2 and
54
-
FPS source is FPS2
55
-
- MAX77620_FPS_SRC_NONE.
56
-
GPIO is not controlled
57
-
by FPS events and it gets
58
-
enabled/disabled by register
59
-
access.
60
-
Absence of this property will leave
61
-
the FPS configuration register for that
62
-
GPIO to default configuration.
63
-
64
-
- maxim,active-fps-power-up-slot: Sequencing event slot number on which
65
-
the GPIO get enabled when
66
-
master FPS input event set to HIGH.
67
-
Valid values are 0 to 7.
68
-
This is applicable if FPS source is
69
-
selected as FPS0, FPS1 or FPS2.
70
-
71
-
- maxim,active-fps-power-down-slot: Sequencing event slot number on which
72
-
the GPIO get disabled when master
73
-
FPS input event set to LOW.
74
-
Valid values are 0 to 7.
75
-
This is applicable if FPS source is
76
-
selected as FPS0, FPS1 or FPS2.
77
-
78
-
- maxim,suspend-fps-source: This is same as property
79
-
"maxim,active-fps-source" but value
80
-
get configured when system enters in
81
-
to suspend state.
82
-
83
-
- maxim,suspend-fps-power-up-slot: This is same as property
84
-
"maxim,active-fps-power-up-slot" but
85
-
this value get configured into FPS
86
-
configuration register when system
87
-
enters into suspend.
88
-
This is applicable if suspend state
89
-
FPS source is selected as FPS0, FPS1 or
90
-
91
-
- maxim,suspend-fps-power-down-slot: This is same as property
92
-
"maxim,active-fps-power-down-slot" but
93
-
this value get configured into FPS
94
-
configuration register when system
95
-
enters into suspend.
96
-
This is applicable if suspend state
97
-
FPS source is selected as FPS0, FPS1 or
98
-
FPS2.
99
-
100
-
Example:
101
-
--------
102
-
#include <dt-bindings/mfd/max77620.h>
103
-
...
104
-
max77620@3c {
105
-
106
-
pinctrl-names = "default";
107
-
pinctrl-0 = <&spmic_default>;
108
-
109
-
spmic_default: pinmux@0 {
110
-
pin_gpio0 {
111
-
pins = "gpio0";
112
-
function = "gpio";
113
-
};
114
-
115
-
pin_gpio1 {
116
-
pins = "gpio1";
117
-
function = "fps-out";
118
-
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
119
-
};
120
-
121
-
pin_gpio2 {
122
-
pins = "gpio2";
123
-
function = "fps-out";
124
-
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
125
-
};
126
-
};
127
-
};
+4
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+4
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+138
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+138
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. Eliza TLMM block
8
+
9
+
maintainers:
10
+
- Abel Vesa <abel.vesa@oss.qualcomm.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,eliza-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 93
31
+
32
+
gpio-line-names:
33
+
maxItems: 185
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-eliza-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-eliza-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-eliza-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$"
61
+
- enum: [ ufs_reset ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
70
+
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl,
71
+
cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx,
72
+
coex_uart2_rx, coex_uart2_tx, dbg_out_clk,
73
+
ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
74
+
ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio,
75
+
gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1,
76
+
hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1,
77
+
hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec,
78
+
host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
79
+
ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out,
80
+
mdp_vsync, mdp_vsync0_out, mdp_vsync11_out,
81
+
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
82
+
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
83
+
pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
84
+
pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
85
+
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk,
86
+
qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
87
+
qlink_big_request, qlink_little_enable,
88
+
qlink_little_request, qlink_wmss, qspi0, qspi_clk,
89
+
qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
90
+
qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
91
+
qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
92
+
qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
93
+
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
94
+
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
95
+
tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,
96
+
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
97
+
uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
98
+
vsense_trigger_mirnat, wcn_sw_ctrl ]
99
+
required:
100
+
- pins
101
+
102
+
required:
103
+
- compatible
104
+
- reg
105
+
106
+
unevaluatedProperties: false
107
+
108
+
examples:
109
+
- |
110
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
111
+
112
+
tlmm: pinctrl@f100000 {
113
+
compatible = "qcom,eliza-tlmm";
114
+
reg = <0x0f100000 0x300000>;
115
+
116
+
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
117
+
118
+
gpio-controller;
119
+
#gpio-cells = <2>;
120
+
121
+
interrupt-controller;
122
+
#interrupt-cells = <2>;
123
+
124
+
gpio-ranges = <&tlmm 0 0 186>;
125
+
126
+
gpio-wo-state {
127
+
pins = "gpio1";
128
+
function = "gpio";
129
+
};
130
+
131
+
qup-uart14-default-state {
132
+
pins = "gpio18", "gpio19";
133
+
function = "qup2_se5";
134
+
drive-strength = <2>;
135
+
bias-disable;
136
+
};
137
+
};
138
+
...
+120
Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml
+120
Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Technologies, Inc. Hawi TLMM block
8
+
9
+
maintainers:
10
+
- Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.
14
+
15
+
allOf:
16
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
+
18
+
properties:
19
+
compatible:
20
+
const: qcom,hawi-tlmm
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
interrupts:
26
+
maxItems: 1
27
+
28
+
gpio-reserved-ranges:
29
+
minItems: 1
30
+
maxItems: 113
31
+
32
+
gpio-line-names:
33
+
maxItems: 226
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-hawi-tlmm-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-hawi-tlmm-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-hawi-tlmm-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
oneOf:
60
+
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
61
+
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
62
+
minItems: 1
63
+
maxItems: 36
64
+
65
+
function:
66
+
description:
67
+
Specify the alternative function to be configured for the specified
68
+
pins.
69
+
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
70
+
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
71
+
cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
72
+
coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
73
+
dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
74
+
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
75
+
ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
76
+
mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
77
+
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
78
+
modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
79
+
nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
80
+
phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
81
+
qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
82
+
qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
83
+
qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
84
+
qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
85
+
qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
86
+
qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
87
+
rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
88
+
sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
89
+
uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
90
+
wcn_sw_ctrl ]
91
+
92
+
required:
93
+
- pins
94
+
95
+
required:
96
+
- compatible
97
+
- reg
98
+
99
+
unevaluatedProperties: false
100
+
101
+
examples:
102
+
- |
103
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
104
+
105
+
tlmm: pinctrl@f100000 {
106
+
compatible = "qcom,hawi-tlmm";
107
+
reg = <0x0f100000 0x300000>;
108
+
interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
109
+
gpio-controller;
110
+
#gpio-cells = <2>;
111
+
gpio-ranges = <&tlmm 0 0 227>;
112
+
interrupt-controller;
113
+
#interrupt-cells = <2>;
114
+
115
+
qup-uart7-state {
116
+
pins = "gpio62", "gpio63";
117
+
function = "qup1_se7";
118
+
};
119
+
};
120
+
...
+123
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
+123
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ5210 TLMM pin controller
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
12
+
13
+
description:
14
+
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
15
+
16
+
allOf:
17
+
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
+
19
+
properties:
20
+
compatible:
21
+
const: qcom,ipq5210-tlmm
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
interrupts:
27
+
maxItems: 1
28
+
29
+
gpio-reserved-ranges:
30
+
minItems: 1
31
+
maxItems: 27
32
+
33
+
gpio-line-names:
34
+
maxItems: 54
35
+
36
+
patternProperties:
37
+
"-state$":
38
+
oneOf:
39
+
- $ref: "#/$defs/qcom-ipq5210-tlmm-state"
40
+
- patternProperties:
41
+
"-pins$":
42
+
$ref: "#/$defs/qcom-ipq5210-tlmm-state"
43
+
additionalProperties: false
44
+
45
+
$defs:
46
+
qcom-ipq5210-tlmm-state:
47
+
type: object
48
+
description:
49
+
Pinctrl node's client devices use subnodes for desired pin configuration.
50
+
Client device subnodes use below standard properties.
51
+
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
52
+
unevaluatedProperties: false
53
+
54
+
properties:
55
+
pins:
56
+
description:
57
+
List of gpio pins affected by the properties specified in this
58
+
subnode.
59
+
items:
60
+
pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
61
+
minItems: 1
62
+
maxItems: 36
63
+
64
+
function:
65
+
description:
66
+
Specify the alternative function to be configured for the specified
67
+
pins.
68
+
69
+
enum: [ atest_char_start, atest_char_status0, atest_char_status1,
70
+
atest_char_status2, atest_char_status3, atest_tic_en, audio_pri,
71
+
audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1,
72
+
audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2,
73
+
audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec,
74
+
audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1,
75
+
audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2,
76
+
audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0,
77
+
cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
78
+
gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0,
79
+
led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst,
80
+
mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n,
81
+
pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test,
82
+
pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx,
83
+
pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los,
84
+
gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0,
85
+
pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
86
+
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
87
+
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
88
+
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
89
+
qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
90
+
qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2,
91
+
qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1,
92
+
rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ]
93
+
94
+
required:
95
+
- pins
96
+
97
+
required:
98
+
- compatible
99
+
- reg
100
+
101
+
unevaluatedProperties: false
102
+
103
+
examples:
104
+
- |
105
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
106
+
107
+
tlmm: pinctrl@1000000 {
108
+
compatible = "qcom,ipq5210-tlmm";
109
+
reg = <0x01000000 0x300000>;
110
+
gpio-controller;
111
+
#gpio-cells = <0x2>;
112
+
gpio-ranges = <&tlmm 0 0 54>;
113
+
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
114
+
interrupt-controller;
115
+
#interrupt-cells = <0x2>;
116
+
117
+
qup-uart1-default-state {
118
+
pins = "gpio38", "gpio39";
119
+
function = "qup_se1";
120
+
drive-strength = <6>;
121
+
bias-pull-down;
122
+
};
123
+
};
+8
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
+8
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
···
27
27
gpio-ranges:
28
28
maxItems: 1
29
29
30
+
gpio-reserved-ranges:
31
+
minItems: 1
32
+
maxItems: 30
33
+
description:
34
+
Pins can be reserved for trusted applications or for LPASS, thereby
35
+
inaccessible from the OS. This property can be used to mark the pins
36
+
which resources should not be accessed by the OS.
37
+
30
38
required:
31
39
- gpio-controller
32
40
- "#gpio-cells"
+109
Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml
+109
Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Milos SoC LPASS LPI TLMM
8
+
9
+
maintainers:
10
+
- Luca Weiss <luca.weiss@fairphone.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm Milos SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,milos-lpass-lpi-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: LPASS LPI TLMM Control and Status registers
23
+
- description: LPASS LPI MCC registers
24
+
25
+
clocks:
26
+
items:
27
+
- description: LPASS Core voting clock
28
+
- description: LPASS Audio voting clock
29
+
30
+
clock-names:
31
+
items:
32
+
- const: core
33
+
- const: audio
34
+
35
+
patternProperties:
36
+
"-state$":
37
+
oneOf:
38
+
- $ref: "#/$defs/qcom-milos-lpass-state"
39
+
- patternProperties:
40
+
"-pins$":
41
+
$ref: "#/$defs/qcom-milos-lpass-state"
42
+
additionalProperties: false
43
+
44
+
$defs:
45
+
qcom-milos-lpass-state:
46
+
type: object
47
+
description:
48
+
Pinctrl node's client devices use subnodes for desired pin configuration.
49
+
Client device subnodes use below standard properties.
50
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
51
+
unevaluatedProperties: false
52
+
53
+
properties:
54
+
pins:
55
+
description:
56
+
List of gpio pins affected by the properties specified in this
57
+
subnode.
58
+
items:
59
+
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
60
+
61
+
function:
62
+
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
63
+
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
64
+
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
65
+
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
66
+
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_clk,
67
+
qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk,
68
+
swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
69
+
wsa_swr_data ]
70
+
description:
71
+
Specify the alternative function to be configured for the specified
72
+
pins.
73
+
74
+
allOf:
75
+
- $ref: qcom,lpass-lpi-common.yaml#
76
+
77
+
required:
78
+
- compatible
79
+
- reg
80
+
- clocks
81
+
- clock-names
82
+
83
+
unevaluatedProperties: false
84
+
85
+
examples:
86
+
- |
87
+
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
88
+
89
+
pinctrl@3440000 {
90
+
compatible = "qcom,milos-lpass-lpi-pinctrl";
91
+
reg = <0x03440000 0x20000>,
92
+
<0x034d0000 0x10000>;
93
+
gpio-controller;
94
+
#gpio-cells = <2>;
95
+
gpio-ranges = <&lpass_tlmm 0 0 23>;
96
+
97
+
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
98
+
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
99
+
clock-names = "core",
100
+
"audio";
101
+
102
+
tx-swr-active-clk-state {
103
+
pins = "gpio0";
104
+
function = "swr_tx_clk";
105
+
drive-strength = <4>;
106
+
slew-rate = <1>;
107
+
bias-disable;
108
+
};
109
+
};
+81
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
+81
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM670 SoC LPASS LPI TLMM
8
+
9
+
maintainers:
10
+
- Richard Acayan <mailingradian@gmail.com>
11
+
12
+
description:
13
+
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
14
+
(LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
15
+
16
+
properties:
17
+
compatible:
18
+
const: qcom,sdm670-lpass-lpi-pinctrl
19
+
20
+
reg:
21
+
items:
22
+
- description: LPASS LPI TLMM Control and Status registers
23
+
24
+
patternProperties:
25
+
"-state$":
26
+
oneOf:
27
+
- $ref: "#/$defs/qcom-sdm670-lpass-state"
28
+
- patternProperties:
29
+
"-pins$":
30
+
$ref: "#/$defs/qcom-sdm670-lpass-state"
31
+
additionalProperties: false
32
+
33
+
$defs:
34
+
qcom-sdm670-lpass-state:
35
+
type: object
36
+
description:
37
+
Pinctrl node's client devices use subnodes for desired pin configuration.
38
+
Client device subnodes use below standard properties.
39
+
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
40
+
unevaluatedProperties: false
41
+
42
+
properties:
43
+
pins:
44
+
description:
45
+
List of gpio pins affected by the properties specified in this
46
+
subnode.
47
+
items:
48
+
pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$"
49
+
50
+
function:
51
+
enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
52
+
i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx,
53
+
pdm_sync, pdm_tx, slimbus_clk ]
54
+
description:
55
+
Specify the alternative function to be configured for the specified
56
+
pins.
57
+
58
+
allOf:
59
+
- $ref: qcom,lpass-lpi-common.yaml#
60
+
61
+
required:
62
+
- compatible
63
+
- reg
64
+
65
+
unevaluatedProperties: false
66
+
67
+
examples:
68
+
- |
69
+
lpi_tlmm: pinctrl@62b40000 {
70
+
compatible = "qcom,sdm670-lpass-lpi-pinctrl";
71
+
reg = <0x62b40000 0x20000>;
72
+
gpio-controller;
73
+
#gpio-cells = <2>;
74
+
gpio-ranges = <&lpi_tlmm 0 0 32>;
75
+
76
+
cdc_comp_default: cdc-comp-default-state {
77
+
pins = "gpio22", "gpio24";
78
+
function = "comp_rx";
79
+
drive-strength = <4>;
80
+
};
81
+
};
+7
-1
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+7
-1
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
···
15
15
16
16
properties:
17
17
compatible:
18
-
const: qcom,sm8450-lpass-lpi-pinctrl
18
+
oneOf:
19
+
- const: qcom,sm8450-lpass-lpi-pinctrl
20
+
- items:
21
+
- enum:
22
+
- qcom,qcs8300-lpass-lpi-pinctrl
23
+
- qcom,sa8775p-lpass-lpi-pinctrl
24
+
- const: qcom,sm8450-lpass-lpi-pinctrl
19
25
20
26
reg:
21
27
items:
+3
-1
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
+3
-1
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
···
135
135
136
136
realtek,duty-cycle:
137
137
description: |
138
-
An integer describing the level to adjust output duty cycle, controlling
139
-
the proportion of positive and negative waveforms in nanoseconds.
138
+
An integer describing the level to adjust the output pulse width, it
139
+
provides a fixed nanosecond-level adjustment to the rising/falling
140
+
edges of an existing signal. It is used for Signal Integrity tuning
141
+
(adding/subtracting delay to fine-tune the high/low duration), rather
142
+
than generating a specific PWM frequency.
140
143
Valid arguments are described as below:
141
144
0: 0ns
142
145
2: + 0.25ns
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
···
134
134
135
135
realtek,duty-cycle:
136
136
description: |
137
-
An integer describing the level to adjust output duty cycle, controlling
138
-
the proportion of positive and negative waveforms in nanoseconds.
137
+
An integer describing the level to adjust the output pulse width, it
138
+
provides a fixed nanosecond-level adjustment to the rising/falling
139
+
edges of an existing signal. It is used for Signal Integrity tuning
140
+
(adding/subtracting delay to fine-tune the high/low duration), rather
141
+
than generating a specific PWM frequency.
139
142
Valid arguments are described as below:
140
143
0: 0ns
141
144
2: + 0.25ns
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
+5
-2
Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
···
133
133
134
134
realtek,duty-cycle:
135
135
description: |
136
-
An integer describing the level to adjust output duty cycle, controlling
137
-
the proportion of positive and negative waveforms in nanoseconds.
136
+
An integer describing the level to adjust the output pulse width, it
137
+
provides a fixed nanosecond-level adjustment to the rising/falling
138
+
edges of an existing signal. It is used for Signal Integrity tuning
139
+
(adding/subtracting delay to fine-tune the high/low duration), rather
140
+
than generating a specific PWM frequency.
138
141
Valid arguments are described as below:
139
142
0: 0ns
140
143
2: + 0.25ns
+260
Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml
+260
Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
# Copyright 2025 Realtek Semiconductor Corporation
3
+
%YAML 1.2
4
+
---
5
+
$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml#
6
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
7
+
8
+
title: Realtek DHC RTD1625 Pin Controller
9
+
10
+
maintainers:
11
+
- Tzuyi Chang <tychang@realtek.com>
12
+
- Yu-Chun Lin <eleanor.lin@realtek.com>
13
+
14
+
description:
15
+
The Realtek DHC RTD1625 is a high-definition media processor SoC. The
16
+
RTD1625 pin controller is used to control pin function, pull-up/down
17
+
resistors, drive strength, slew rate, Schmitt trigger, power source
18
+
(I/O output voltage), input threshold domain selection and a higher-VIL mode.
19
+
20
+
properties:
21
+
compatible:
22
+
items:
23
+
- enum:
24
+
- realtek,rtd1625-iso-pinctrl
25
+
- realtek,rtd1625-main2-pinctrl
26
+
- realtek,rtd1625-isom-pinctrl
27
+
- realtek,rtd1625-ve4-pinctrl
28
+
29
+
reg:
30
+
maxItems: 1
31
+
32
+
patternProperties:
33
+
'-pins$':
34
+
type: object
35
+
allOf:
36
+
- $ref: pincfg-node.yaml#
37
+
- $ref: pinmux-node.yaml#
38
+
39
+
properties:
40
+
pins:
41
+
items:
42
+
enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6,
43
+
gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13,
44
+
gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20,
45
+
gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29,
46
+
gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40,
47
+
gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47,
48
+
gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54,
49
+
gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61,
50
+
gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80,
51
+
gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87,
52
+
gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94,
53
+
gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100,
54
+
gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106,
55
+
gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112,
56
+
gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133,
57
+
gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139,
58
+
gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145,
59
+
gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151,
60
+
gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157,
61
+
gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163,
62
+
gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en,
63
+
csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc,
64
+
ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk,
65
+
emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3,
66
+
emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7,
67
+
emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data,
68
+
hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel,
69
+
sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2,
70
+
ve4_uart_loc]
71
+
72
+
function:
73
+
enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0,
74
+
ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8,
75
+
csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc,
76
+
gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1,
77
+
i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl,
78
+
pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5,
79
+
rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable,
80
+
spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1,
81
+
uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10,
82
+
usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic,
83
+
vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1,
84
+
ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1,
85
+
etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1,
86
+
i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0,
87
+
pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0,
88
+
pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1,
89
+
uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1,
90
+
ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2,
91
+
aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2,
92
+
aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2,
93
+
aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0,
94
+
pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2,
95
+
scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2,
96
+
ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0,
97
+
pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable,
98
+
arm_trace_debug_enable]
99
+
100
+
drive-strength:
101
+
enum: [4, 8]
102
+
103
+
bias-pull-down: true
104
+
105
+
bias-pull-up: true
106
+
107
+
bias-disable: true
108
+
109
+
input-schmitt-enable: true
110
+
111
+
input-schmitt-disable: true
112
+
113
+
input-voltage-microvolt:
114
+
description: |
115
+
Select the input receiver voltage domain for the pin.
116
+
Valid arguments are:
117
+
- 1800000: 1.8V input logic level
118
+
- 3300000: 3.3V input logic level
119
+
enum: [1800000, 3300000]
120
+
121
+
drive-push-pull: true
122
+
123
+
power-source:
124
+
description: |
125
+
Valid arguments are described as below:
126
+
0: power supply of 1.8V
127
+
1: power supply of 3.3V
128
+
enum: [0, 1]
129
+
130
+
slew-rate:
131
+
description: |
132
+
Valid arguments are described as below:
133
+
1: ~1ns falling time
134
+
10: ~10ns falling time
135
+
20: ~20ns falling time
136
+
30: ~30ns falling time
137
+
enum: [1, 10, 20, 30]
138
+
139
+
realtek,drive-strength-p:
140
+
description: |
141
+
Some of pins can be driven using the P-MOS and N-MOS transistor to
142
+
achieve finer adjustments. The block-diagram representation is as
143
+
follows:
144
+
VDD
145
+
|
146
+
||--+
147
+
+-----o|| P-MOS-FET
148
+
| ||--+
149
+
IN --+ +----- out
150
+
| ||--+
151
+
+------|| N-MOS-FET
152
+
||--+
153
+
|
154
+
GND
155
+
The driving strength of the P-MOS/N-MOS transistors impacts the
156
+
waveform's rise/fall times. Greater driving strength results in
157
+
shorter rise/fall times. Each P-MOS and N-MOS transistor offers
158
+
8 configurable levels (0 to 7), with higher values indicating
159
+
greater driving strength, contributing to achieving the desired
160
+
speed.
161
+
162
+
The realtek,drive-strength-p is used to control the driving strength
163
+
of the P-MOS output.
164
+
165
+
This value is not a simple count of transistors. Instead, it
166
+
represents a weighted configuration. There is a base driving
167
+
capability (even at value 0), and each bit adds a different weight to
168
+
the total strength. The resulting current is non-linear and varies
169
+
significantly based on the IO voltage (1.8V vs 3.3V) and the specific
170
+
pad group.
171
+
$ref: /schemas/types.yaml#/definitions/uint32
172
+
minimum: 0
173
+
maximum: 7
174
+
175
+
realtek,drive-strength-n:
176
+
description: |
177
+
Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
178
+
is used to control the driving strength of the N-MOS output.
179
+
180
+
This property uses the same weighted configuration logic where values
181
+
0-7 represent non-linear strength adjustments rather than a transistor
182
+
count.
183
+
184
+
Higher values indicate greater driving strength, resulting in shorter
185
+
fall times.
186
+
$ref: /schemas/types.yaml#/definitions/uint32
187
+
minimum: 0
188
+
maximum: 7
189
+
190
+
realtek,duty-cycle:
191
+
description: |
192
+
An integer describing the level to adjust the output pulse width, it
193
+
provides a fixed nanosecond-level adjustment to the rising/falling
194
+
edges of an existing signal. It is used for Signal Integrity tuning
195
+
(adding/subtracting delay to fine-tune the high/low duration), rather
196
+
than generating a specific PWM frequency.
197
+
198
+
Valid arguments are described as below:
199
+
0: 0ns
200
+
2: + 0.25ns
201
+
3: + 0.5ns
202
+
4: -0.25ns
203
+
5: -0.5ns
204
+
$ref: /schemas/types.yaml#/definitions/uint32
205
+
enum: [0, 2, 3, 4, 5]
206
+
207
+
realtek,high-vil-microvolt:
208
+
description: |
209
+
The threshold value for the input receiver's LOW recognition (VIL).
210
+
211
+
This property is used to address specific HDMI I2C compatibility
212
+
issues where some sinks (TVs) have weak pull-down capabilities and
213
+
fail to pull the bus voltage below the standard VIL threshold
214
+
(~0.7V).
215
+
216
+
Setting this property to 1100000 (1.1V) enables a specialized input
217
+
receiver mode that raises the effective VIL threshold to improve
218
+
detection.
219
+
enum: [1100000]
220
+
221
+
required:
222
+
- pins
223
+
224
+
additionalProperties: false
225
+
226
+
required:
227
+
- compatible
228
+
- reg
229
+
230
+
additionalProperties: false
231
+
232
+
examples:
233
+
- |
234
+
pinctrl@4e000 {
235
+
compatible = "realtek,rtd1625-iso-pinctrl";
236
+
reg = <0x4e000 0x130>;
237
+
238
+
emmc-hs200-pins {
239
+
pins = "emmc_clk",
240
+
"emmc_cmd",
241
+
"emmc_data_0",
242
+
"emmc_data_1",
243
+
"emmc_data_2",
244
+
"emmc_data_3",
245
+
"emmc_data_4",
246
+
"emmc_data_5",
247
+
"emmc_data_6",
248
+
"emmc_data_7";
249
+
function = "emmc";
250
+
realtek,drive-strength-p = <2>;
251
+
realtek,drive-strength-n = <2>;
252
+
};
253
+
254
+
i2c-0-pins {
255
+
pins = "gpio_12",
256
+
"gpio_13";
257
+
function = "i2c0";
258
+
drive-strength = <4>;
259
+
};
260
+
};
+17
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+17
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
···
83
83
input: true
84
84
input-enable: true
85
85
output-enable: true
86
+
bias-disable: true
87
+
bias-pull-down: true
88
+
bias-pull-up: true
89
+
input-schmitt-enable: true
90
+
input-schmitt-disable: true
91
+
slew-rate:
92
+
description: 0 is slow slew rate, 1 is fast slew rate
93
+
enum: [0, 1]
94
+
drive-strength-microamp:
95
+
description: |
96
+
Four discrete levels are supported (via registers DRCTLm), corresponding
97
+
to the following nominal values:
98
+
- 2500 (Low strength)
99
+
- 5000 (Middle strength)
100
+
- 9000 (High strength)
101
+
- 11800 (Ultra High strength)
102
+
enum: [2500, 5000, 9000, 11800]
86
103
oneOf:
87
104
- required: [pinmux]
88
105
- required: [pins]
+1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+1
-1
drivers/gpio/gpio-rockchip.c
+1
-1
drivers/gpio/gpio-rockchip.c
+1
drivers/gpio/gpio-spacemit-k1.c
+1
drivers/gpio/gpio-spacemit-k1.c
+1
-10
drivers/pinctrl/Kconfig
+1
-10
drivers/pinctrl/Kconfig
···
77
77
select GPIOLIB_IRQCHIP
78
78
select GENERIC_PINCTRL_GROUPS
79
79
select GENERIC_PINMUX_FUNCTIONS
80
-
select OF_GPIO
81
80
help
82
81
This is the driver for the GPIO controller found on Apple ARM SoCs,
83
82
including M1.
···
125
126
select GENERIC_PINCONF
126
127
select GPIOLIB
127
128
select GPIOLIB_IRQCHIP
128
-
select OF_GPIO
129
129
help
130
130
Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
131
131
controller available on sama5d2 SoC.
···
291
293
select GENERIC_PINMUX_FUNCTIONS
292
294
select GENERIC_PINCONF
293
295
select GPIOLIB
294
-
select OF_GPIO
295
296
select REGMAP_MMIO
296
297
default SOC_CANAAN_K210
297
298
help
···
416
419
select GENERIC_PINCONF
417
420
select GENERIC_PINCTRL_GROUPS
418
421
select GENERIC_PINMUX_FUNCTIONS
419
-
select OF_GPIO
420
422
help
421
423
Support for the serial GPIO interface used on Microsemi and
422
424
Microchip SoCs. By using a serial interface, the SIO
···
437
441
select GENERIC_PINCONF
438
442
select GENERIC_PINCTRL_GROUPS
439
443
select GENERIC_PINMUX_FUNCTIONS
440
-
select OF_GPIO
441
444
select REGMAP_MMIO
442
445
help
443
446
Support for the internal GPIO interfaces on Microsemi Ocelot and
···
473
478
config PINCTRL_PIC32
474
479
bool "Microchip PIC32 pin controller driver"
475
480
depends on OF
476
-
depends on MACH_PIC32
481
+
depends on MACH_PIC32 || COMPILE_TEST
477
482
select PINMUX
478
483
select GENERIC_PINCONF
479
484
select GPIOLIB_IRQCHIP
480
-
select OF_GPIO
481
485
help
482
486
This is the pin controller and gpio driver for Microchip PIC32
483
487
microcontrollers. This option is selected automatically when specific
···
493
499
select PINMUX
494
500
select GENERIC_PINCONF
495
501
select GPIOLIB_IRQCHIP
496
-
select OF_GPIO
497
502
help
498
503
This support pinctrl and GPIO driver for IMG Pistachio SoC.
499
504
···
514
521
select GENERIC_PINCONF
515
522
select GENERIC_IRQ_CHIP
516
523
select MFD_SYSCON
517
-
select OF_GPIO
518
524
default ARCH_ROCKCHIP
519
525
help
520
526
This support pinctrl and GPIO driver for Rockchip SoCs.
···
549
557
config PINCTRL_STMFX
550
558
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
551
559
depends on I2C
552
-
depends on OF_GPIO
553
560
depends on HAS_IOMEM
554
561
select GENERIC_PINCONF
555
562
select GPIOLIB_IRQCHIP
+2
-2
drivers/pinctrl/bcm/Kconfig
+2
-2
drivers/pinctrl/bcm/Kconfig
···
120
120
121
121
config PINCTRL_IPROC_GPIO
122
122
bool "Broadcom iProc GPIO (with PINCONF) driver"
123
-
depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
123
+
depends on ARCH_BCM_IPROC || COMPILE_TEST
124
124
select GPIOLIB_IRQCHIP
125
125
select PINCONF
126
126
select GENERIC_PINCONF
···
185
185
186
186
config PINCTRL_NSP_GPIO
187
187
bool "Broadcom NSP GPIO (with PINCONF) driver"
188
-
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
188
+
depends on ARCH_BCM_NSP || COMPILE_TEST
189
189
select GPIOLIB_IRQCHIP
190
190
select PINCONF
191
191
select GENERIC_PINCONF
+4
-3
drivers/pinctrl/core.c
+4
-3
drivers/pinctrl/core.c
···
24
24
#include <linux/seq_file.h>
25
25
#include <linux/slab.h>
26
26
27
-
#include <linux/gpio.h>
27
+
#include <linux/gpio/consumer.h>
28
28
#include <linux/gpio/driver.h>
29
29
30
30
#include <linux/pinctrl/consumer.h>
···
1381
1381
goto restore_old_state;
1382
1382
1383
1383
unapply_new_state:
1384
-
dev_err(p->dev, "Error applying setting, reverse things back\n");
1384
+
dev_err_probe(p->dev, ret,
1385
+
"Error applying setting, reverse things back\n");
1385
1386
1386
1387
/*
1387
1388
* All we can do here is pinmux_disable_setting.
···
2023
2022
device_root = debugfs_create_dir(debugfs_name, debugfs_root);
2024
2023
pctldev->device_root = device_root;
2025
2024
2026
-
if (IS_ERR(device_root) || !device_root) {
2025
+
if (IS_ERR_OR_NULL(device_root)) {
2027
2026
pr_warn("failed to create debugfs directory for %s\n",
2028
2027
dev_name(pctldev->dev));
2029
2028
return;
+1
-1
drivers/pinctrl/devicetree.c
+1
-1
drivers/pinctrl/devicetree.c
+1
-1
drivers/pinctrl/freescale/Kconfig
+1
-1
drivers/pinctrl/freescale/Kconfig
···
9
9
10
10
config PINCTRL_IMX_SCMI
11
11
tristate "i.MX95 pinctrl driver using SCMI protocol interface"
12
-
depends on ARM_SCMI_PROTOCOL && OF
12
+
depends on (ARM_SCMI_PROTOCOL && OF && ARCH_MXC) || COMPILE_TEST
13
13
select PINMUX
14
14
select GENERIC_PINCONF
15
15
select GENERIC_PINCTRL_GROUPS
-1
drivers/pinctrl/meson/Kconfig
-1
drivers/pinctrl/meson/Kconfig
+1
-1
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
+1
-1
drivers/pinctrl/microchip/pinctrl-mpfs-mssio.c
···
686
686
687
687
pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
688
688
if (IS_ERR(pctrl->regmap))
689
-
dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
689
+
return dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
690
690
691
691
pctrl->sysreg_regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-sysreg-scb");
692
692
if (IS_ERR(pctrl->sysreg_regmap))
+1
-1
drivers/pinctrl/nomadik/pinctrl-abx500.c
+1
-1
drivers/pinctrl/nomadik/pinctrl-abx500.c
+1
-1
drivers/pinctrl/nxp/pinctrl-s32.h
+1
-1
drivers/pinctrl/nxp/pinctrl-s32.h
···
16
16
/**
17
17
* struct s32_pin_group - describes an S32 pin group
18
18
* @data: generic data describes group name, number of pins, and a pin array in
19
-
this group.
19
+
* this group.
20
20
* @pin_sss: an array of source signal select configs paired with pin array.
21
21
*/
22
22
struct s32_pin_group {
+71
-23
drivers/pinctrl/pinconf-generic.c
+71
-23
drivers/pinctrl/pinconf-generic.c
···
16
16
#include <linux/init.h>
17
17
#include <linux/module.h>
18
18
#include <linux/of.h>
19
+
#include <linux/property.h>
19
20
#include <linux/slab.h>
20
21
#include <linux/seq_file.h>
21
22
···
57
56
PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
58
57
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_INPUT_PS, "input skew delay", "ps", true),
59
58
PCONFDUMP(PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, "output skew delay", "ps", true),
59
+
PCONFDUMP(PIN_CONFIG_INPUT_VOLTAGE_UV, "input voltage in microvolt", "uV", true),
60
60
};
61
61
62
62
static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
···
204
202
{ "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
205
203
{ "skew-delay-input-ps", PIN_CONFIG_SKEW_DELAY_INPUT_PS, 0 },
206
204
{ "skew-delay-output-ps", PIN_CONFIG_SKEW_DELAY_OUTPUT_PS, 0 },
205
+
{ "input-threshold-voltage-microvolt", PIN_CONFIG_INPUT_VOLTAGE_UV, 0 },
207
206
};
208
207
209
208
/**
210
-
* parse_dt_cfg() - Parse DT pinconf parameters
211
-
* @np: DT node
209
+
* parse_fw_cfg() - Parse firmware pinconf parameters
210
+
* @fwnode: firmware node
212
211
* @params: Array of describing generic parameters
213
212
* @count: Number of entries in @params
214
213
* @cfg: Array of parsed config options
215
214
* @ncfg: Number of entries in @cfg
216
215
*
217
-
* Parse the config options described in @params from @np and puts the result
216
+
* Parse the config options described in @params from @fwnode and puts the result
218
217
* in @cfg. @cfg does not need to be empty, entries are added beginning at
219
218
* @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
220
219
* needs to have enough memory allocated to hold all possible entries.
221
220
*/
222
-
static int parse_dt_cfg(struct device_node *np,
221
+
static int parse_fw_cfg(struct fwnode_handle *fwnode,
223
222
const struct pinconf_generic_params *params,
224
223
unsigned int count, unsigned long *cfg,
225
224
unsigned int *ncfg)
226
225
{
227
-
int i;
226
+
unsigned long *properties;
227
+
int i, test;
228
+
229
+
properties = bitmap_zalloc(count, GFP_KERNEL);
228
230
229
231
for (i = 0; i < count; i++) {
230
232
u32 val;
···
236
230
const struct pinconf_generic_params *par = ¶ms[i];
237
231
238
232
if (par->values && par->num_values) {
239
-
ret = fwnode_property_match_property_string(of_fwnode_handle(np),
233
+
ret = fwnode_property_match_property_string(fwnode,
240
234
par->property,
241
235
par->values, par->num_values);
242
236
if (ret == -ENOENT)
···
246
240
ret = 0;
247
241
}
248
242
} else {
249
-
ret = of_property_read_u32(np, par->property, &val);
243
+
ret = fwnode_property_read_u32(fwnode, par->property, &val);
250
244
}
251
245
252
246
/* property not found */
···
257
251
if (ret)
258
252
val = par->default_value;
259
253
254
+
/* if param is greater than count, these are custom properties */
255
+
if (par->param <= count) {
256
+
ret = test_and_set_bit(par->param, properties);
257
+
if (ret) {
258
+
pr_err("%pfw: conflicting setting detected for %s\n",
259
+
fwnode, par->property);
260
+
bitmap_free(properties);
261
+
return -EINVAL;
262
+
}
263
+
}
264
+
260
265
pr_debug("found %s with value %u\n", par->property, val);
261
266
cfg[*ncfg] = pinconf_to_config_packed(par->param, val);
262
267
(*ncfg)++;
263
268
}
264
269
270
+
if (test_bit(PIN_CONFIG_DRIVE_STRENGTH, properties) &&
271
+
test_bit(PIN_CONFIG_DRIVE_STRENGTH_UA, properties))
272
+
pr_err("%pfw: cannot have multiple drive strength properties\n",
273
+
fwnode);
274
+
275
+
test = test_bit(PIN_CONFIG_BIAS_BUS_HOLD, properties) +
276
+
test_bit(PIN_CONFIG_BIAS_DISABLE, properties) +
277
+
test_bit(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, properties) +
278
+
test_bit(PIN_CONFIG_BIAS_PULL_UP, properties) +
279
+
test_bit(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, properties) +
280
+
test_bit(PIN_CONFIG_BIAS_PULL_DOWN, properties);
281
+
if (test > 1)
282
+
pr_err("%pfw: cannot have multiple bias configurations\n",
283
+
fwnode);
284
+
285
+
test = test_bit(PIN_CONFIG_DRIVE_OPEN_DRAIN, properties) +
286
+
test_bit(PIN_CONFIG_DRIVE_OPEN_SOURCE, properties) +
287
+
test_bit(PIN_CONFIG_DRIVE_PUSH_PULL, properties);
288
+
if (test > 1)
289
+
pr_err("%pfw: cannot have multiple drive configurations\n",
290
+
fwnode);
291
+
292
+
bitmap_free(properties);
265
293
return 0;
266
294
}
267
295
···
314
274
unsigned int **pid, unsigned int **pmux,
315
275
unsigned int *npins)
316
276
{
277
+
struct fwnode_handle *fwnode = of_fwnode_handle(np);
317
278
unsigned int *pid_t;
318
279
unsigned int *pmux_t;
319
-
struct property *prop;
320
280
unsigned int npins_t, i;
321
-
u32 value;
322
281
int ret;
323
282
324
-
prop = of_find_property(np, "pinmux", NULL);
325
-
if (!prop) {
283
+
ret = fwnode_property_count_u32(fwnode, "pinmux");
284
+
if (ret < 0) {
326
285
dev_info(dev, "Missing pinmux property\n");
327
-
return -ENOENT;
286
+
return ret;
287
+
}
288
+
289
+
npins_t = ret;
290
+
if (npins_t == 0) {
291
+
dev_info(dev, "pinmux property doesn't have entries\n");
292
+
return -ENODATA;
328
293
}
329
294
330
295
if (!pid || !pmux || !npins) {
···
337
292
return -EINVAL;
338
293
}
339
294
340
-
npins_t = prop->length / sizeof(u32);
341
295
pid_t = devm_kcalloc(dev, npins_t, sizeof(*pid_t), GFP_KERNEL);
342
296
pmux_t = devm_kcalloc(dev, npins_t, sizeof(*pmux_t), GFP_KERNEL);
343
297
if (!pid_t || !pmux_t) {
344
298
dev_err(dev, "kalloc memory fail\n");
345
299
return -ENOMEM;
346
300
}
301
+
302
+
ret = fwnode_property_read_u32_array(fwnode, "pinmux", pmux_t, npins_t);
303
+
if (ret) {
304
+
dev_err(dev, "get pinmux value fail\n");
305
+
goto exit;
306
+
}
307
+
347
308
for (i = 0; i < npins_t; i++) {
348
-
ret = of_property_read_u32_index(np, "pinmux", i, &value);
349
-
if (ret) {
350
-
dev_err(dev, "get pinmux value fail\n");
351
-
goto exit;
352
-
}
353
-
pmux_t[i] = value & 0xff;
354
-
pid_t[i] = (value >> 8) & 0xffffff;
309
+
pid_t[i] = pmux_t[i] >> 8;
310
+
pmux_t[i] = pmux_t[i] & 0xff;
355
311
}
356
312
*pid = pid_t;
357
313
*pmux = pmux_t;
···
382
336
{
383
337
unsigned long *cfg;
384
338
unsigned int max_cfg, ncfg = 0;
339
+
struct fwnode_handle *fwnode;
385
340
int ret;
386
341
387
-
if (!np)
342
+
fwnode = of_fwnode_handle(np);
343
+
if (!fwnode)
388
344
return -EINVAL;
389
345
390
346
/* allocate a temporary array big enough to hold one of each option */
···
397
349
if (!cfg)
398
350
return -ENOMEM;
399
351
400
-
ret = parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
352
+
ret = parse_fw_cfg(fwnode, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
401
353
if (ret)
402
354
goto out;
403
355
if (pctldev && pctldev->desc->num_custom_params &&
404
356
pctldev->desc->custom_params) {
405
-
ret = parse_dt_cfg(np, pctldev->desc->custom_params,
357
+
ret = parse_fw_cfg(fwnode, pctldev->desc->custom_params,
406
358
pctldev->desc->num_custom_params, cfg, &ncfg);
407
359
if (ret)
408
360
goto out;
+1
drivers/pinctrl/pinctrl-amd.c
+1
drivers/pinctrl/pinctrl-amd.c
+38
-55
drivers/pinctrl/pinctrl-cy8c95x0.c
+38
-55
drivers/pinctrl/pinctrl-cy8c95x0.c
···
72
72
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
73
73
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
74
74
75
-
static const struct i2c_device_id cy8c95x0_id[] = {
76
-
{ "cy8c9520", 20, },
77
-
{ "cy8c9540", 40, },
78
-
{ "cy8c9560", 60, },
79
-
{ }
80
-
};
81
-
MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
82
-
83
-
#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
84
-
85
-
static const struct of_device_id cy8c95x0_dt_ids[] = {
86
-
{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20), },
87
-
{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40), },
88
-
{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60), },
89
-
{ }
90
-
};
91
-
MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
92
-
93
75
static const struct acpi_gpio_params cy8c95x0_irq_gpios = { 0, 0, true };
94
76
95
77
static const struct acpi_gpio_mapping cy8c95x0_acpi_irq_gpios[] = {
···
126
144
* @map: Mask used to compensate for Gport2 width
127
145
* @nport: Number of Gports in this chip
128
146
* @gpio_chip: gpiolib chip
129
-
* @driver_data: private driver data
130
147
* @dev: struct device
131
148
* @pctldev: pin controller device
132
149
* @pinctrl_desc: pin controller description
133
-
* @name: Chip controller name
134
150
* @tpin: Total number of pins
135
151
* @gpio_reset: GPIO line handler that can reset the IC
136
152
*/
···
145
165
DECLARE_BITMAP(map, MAX_LINE);
146
166
unsigned int nport;
147
167
struct gpio_chip gpio_chip;
148
-
unsigned long driver_data;
149
168
struct device *dev;
150
169
struct pinctrl_dev *pctldev;
151
170
struct pinctrl_desc pinctrl_desc;
152
-
char name[32];
153
171
unsigned int tpin;
154
172
struct gpio_desc *gpio_reset;
155
173
};
···
1288
1310
{
1289
1311
struct gpio_irq_chip *girq = &chip->gpio_chip.irq;
1290
1312
DECLARE_BITMAP(pending_irqs, MAX_LINE);
1313
+
struct device *dev = chip->dev;
1291
1314
int ret;
1292
1315
1293
-
mutex_init(&chip->irq_lock);
1316
+
ret = devm_mutex_init(chip->dev, &chip->irq_lock);
1317
+
if (ret)
1318
+
return ret;
1294
1319
1295
1320
bitmap_zero(pending_irqs, MAX_LINE);
1296
1321
1297
1322
/* Read IRQ status register to clear all pending interrupts */
1298
1323
ret = cy8c95x0_irq_pending(chip, pending_irqs);
1299
-
if (ret) {
1300
-
dev_err(chip->dev, "failed to clear irq status register\n");
1301
-
return ret;
1302
-
}
1324
+
if (ret)
1325
+
return dev_err_probe(dev, -EBUSY, "failed to clear irq status register\n");
1303
1326
1304
1327
/* Mask all interrupts */
1305
1328
bitmap_fill(chip->irq_mask, MAX_LINE);
···
1315
1336
girq->handler = handle_simple_irq;
1316
1337
girq->threaded = true;
1317
1338
1318
-
ret = devm_request_threaded_irq(chip->dev, irq,
1319
-
NULL, cy8c95x0_irq_handler,
1320
-
IRQF_ONESHOT | IRQF_SHARED,
1321
-
dev_name(chip->dev), chip);
1322
-
if (ret) {
1323
-
dev_err(chip->dev, "failed to request irq %d\n", irq);
1324
-
return ret;
1325
-
}
1326
-
dev_info(chip->dev, "Registered threaded IRQ\n");
1327
-
1328
-
return 0;
1339
+
return devm_request_threaded_irq(dev, irq, NULL, cy8c95x0_irq_handler,
1340
+
IRQF_ONESHOT | IRQF_SHARED,
1341
+
dev_name(chip->dev), chip);
1329
1342
}
1330
1343
1331
1344
static int cy8c95x0_setup_pinctrl(struct cy8c95x0_pinctrl *chip)
···
1333
1362
pd->owner = THIS_MODULE;
1334
1363
1335
1364
chip->pctldev = devm_pinctrl_register(chip->dev, pd, chip);
1336
-
if (IS_ERR(chip->pctldev))
1337
-
return dev_err_probe(chip->dev, PTR_ERR(chip->pctldev),
1338
-
"can't register controller\n");
1339
-
1340
-
return 0;
1365
+
return PTR_ERR_OR_ZERO(chip->pctldev);
1341
1366
}
1342
1367
1343
1368
static int cy8c95x0_detect(struct i2c_client *client,
···
1351
1384
return ret;
1352
1385
switch (ret & GENMASK(7, 4)) {
1353
1386
case 0x20:
1354
-
name = cy8c95x0_id[0].name;
1387
+
name = "cy8c9520";
1355
1388
break;
1356
1389
case 0x40:
1357
-
name = cy8c95x0_id[1].name;
1390
+
name = "cy8c9540";
1358
1391
break;
1359
1392
case 0x60:
1360
-
name = cy8c95x0_id[2].name;
1393
+
name = "cy8c9560";
1361
1394
break;
1362
1395
default:
1363
1396
return -ENODEV;
···
1375
1408
struct cy8c95x0_pinctrl *chip;
1376
1409
struct regmap_config regmap_conf;
1377
1410
struct regmap_range_cfg regmap_range_conf;
1411
+
unsigned long driver_data;
1378
1412
int ret;
1379
1413
1380
1414
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
···
1385
1417
chip->dev = dev;
1386
1418
1387
1419
/* Set the device type */
1388
-
chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1389
-
if (!chip->driver_data)
1390
-
return -ENODEV;
1420
+
driver_data = (unsigned long)i2c_get_match_data(client);
1391
1421
1392
-
chip->tpin = chip->driver_data & CY8C95X0_GPIO_MASK;
1422
+
chip->tpin = driver_data & CY8C95X0_GPIO_MASK;
1393
1423
chip->nport = DIV_ROUND_UP(CY8C95X0_PIN_TO_OFFSET(chip->tpin), BANK_SZ);
1394
1424
1395
1425
memcpy(®map_range_conf, &cy8c95x0_ranges[0], sizeof(regmap_range_conf));
1396
1426
1397
1427
switch (chip->tpin) {
1398
1428
case 20:
1399
-
strscpy(chip->name, cy8c95x0_id[0].name);
1400
1429
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 3 * MUXED_STRIDE - 1;
1401
1430
break;
1402
1431
case 40:
1403
-
strscpy(chip->name, cy8c95x0_id[1].name);
1404
1432
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 6 * MUXED_STRIDE - 1;
1405
1433
break;
1406
1434
case 60:
1407
-
strscpy(chip->name, cy8c95x0_id[2].name);
1408
1435
regmap_range_conf.range_max = CY8C95X0_VIRTUAL + 8 * MUXED_STRIDE - 1;
1409
1436
break;
1410
1437
default:
···
1437
1474
bitmap_fill(chip->map, MAX_LINE);
1438
1475
bitmap_clear(chip->map, 20, 4);
1439
1476
1440
-
mutex_init(&chip->i2c_lock);
1477
+
ret = devm_mutex_init(dev, &chip->i2c_lock);
1478
+
if (ret)
1479
+
return ret;
1441
1480
1442
1481
if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
1443
1482
ret = cy8c95x0_acpi_get_irq(&client->dev);
···
1460
1495
return cy8c95x0_setup_gpiochip(chip);
1461
1496
}
1462
1497
1498
+
static const struct i2c_device_id cy8c95x0_id[] = {
1499
+
{ "cy8c9520", 20 },
1500
+
{ "cy8c9540", 40 },
1501
+
{ "cy8c9560", 60 },
1502
+
{ }
1503
+
};
1504
+
MODULE_DEVICE_TABLE(i2c, cy8c95x0_id);
1505
+
1506
+
#define OF_CY8C95X(__nrgpio) ((void *)(__nrgpio))
1507
+
1508
+
static const struct of_device_id cy8c95x0_dt_ids[] = {
1509
+
{ .compatible = "cypress,cy8c9520", .data = OF_CY8C95X(20) },
1510
+
{ .compatible = "cypress,cy8c9540", .data = OF_CY8C95X(40) },
1511
+
{ .compatible = "cypress,cy8c9560", .data = OF_CY8C95X(60) },
1512
+
{ }
1513
+
};
1514
+
MODULE_DEVICE_TABLE(of, cy8c95x0_dt_ids);
1515
+
1463
1516
static const struct acpi_device_id cy8c95x0_acpi_ids[] = {
1464
-
{ "INT3490", 40, },
1517
+
{ "INT3490", 40 },
1465
1518
{ }
1466
1519
};
1467
1520
MODULE_DEVICE_TABLE(acpi, cy8c95x0_acpi_ids);
+26
-38
drivers/pinctrl/pinctrl-pic32.c
+26
-38
drivers/pinctrl/pinctrl-pic32.c
···
1696
1696
}
1697
1697
1698
1698
static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
1699
-
unsigned pin)
1699
+
unsigned int pin)
1700
1700
{
1701
1701
return &pctl->gpio_banks[pin / PINS_PER_BANK];
1702
1702
}
···
1709
1709
}
1710
1710
1711
1711
static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
1712
-
unsigned group)
1712
+
unsigned int group)
1713
1713
{
1714
1714
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1715
1715
···
1717
1717
}
1718
1718
1719
1719
static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
1720
-
unsigned group,
1721
-
const unsigned **pins,
1722
-
unsigned *num_pins)
1720
+
unsigned int group,
1721
+
const unsigned int **pins,
1722
+
unsigned int *num_pins)
1723
1723
{
1724
1724
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1725
1725
···
1745
1745
}
1746
1746
1747
1747
static const char *
1748
-
pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
1748
+
pic32_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
1749
1749
{
1750
1750
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1751
1751
···
1753
1753
}
1754
1754
1755
1755
static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
1756
-
unsigned func,
1756
+
unsigned int func,
1757
1757
const char * const **groups,
1758
-
unsigned * const num_groups)
1758
+
unsigned int * const num_groups)
1759
1759
{
1760
1760
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1761
1761
···
1766
1766
}
1767
1767
1768
1768
static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,
1769
-
unsigned func, unsigned group)
1769
+
unsigned int func, unsigned int group)
1770
1770
{
1771
1771
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1772
1772
const struct pic32_pin_group *pg = &pctl->groups[group];
···
1795
1795
1796
1796
static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,
1797
1797
struct pinctrl_gpio_range *range,
1798
-
unsigned offset)
1798
+
unsigned int offset)
1799
1799
{
1800
1800
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1801
1801
struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);
···
1810
1810
}
1811
1811
1812
1812
static int pic32_gpio_direction_input(struct gpio_chip *chip,
1813
-
unsigned offset)
1813
+
unsigned int offset)
1814
1814
{
1815
1815
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
1816
1816
u32 mask = BIT(offset);
···
1820
1820
return 0;
1821
1821
}
1822
1822
1823
-
static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)
1823
+
static int pic32_gpio_get(struct gpio_chip *chip, unsigned int offset)
1824
1824
{
1825
1825
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
1826
1826
···
1842
1842
}
1843
1843
1844
1844
static int pic32_gpio_direction_output(struct gpio_chip *chip,
1845
-
unsigned offset, int value)
1845
+
unsigned int offset, int value)
1846
1846
{
1847
1847
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
1848
1848
u32 mask = BIT(offset);
···
1855
1855
1856
1856
static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,
1857
1857
struct pinctrl_gpio_range *range,
1858
-
unsigned offset, bool input)
1858
+
unsigned int offset, bool input)
1859
1859
{
1860
1860
struct gpio_chip *chip = range->gc;
1861
1861
···
1876
1876
.gpio_set_direction = pic32_gpio_set_direction,
1877
1877
};
1878
1878
1879
-
static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
1879
+
static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1880
1880
unsigned long *config)
1881
1881
{
1882
1882
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1883
1883
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
1884
-
unsigned param = pinconf_to_config_param(*config);
1884
+
unsigned int param = pinconf_to_config_param(*config);
1885
1885
u32 mask = BIT(pin - bank->gpio_chip.base);
1886
1886
u32 arg;
1887
1887
···
1917
1917
return 0;
1918
1918
}
1919
1919
1920
-
static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1921
-
unsigned long *configs, unsigned num_configs)
1920
+
static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1921
+
unsigned long *configs, unsigned int num_configs)
1922
1922
{
1923
1923
struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1924
1924
struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
1925
-
unsigned param;
1925
+
unsigned int param;
1926
1926
u32 arg;
1927
1927
unsigned int i;
1928
1928
u32 offset = pin - bank->gpio_chip.base;
···
1938
1938
switch (param) {
1939
1939
case PIN_CONFIG_BIAS_PULL_UP:
1940
1940
dev_dbg(pctl->dev, " pullup\n");
1941
-
writel(mask, bank->reg_base +PIC32_SET(CNPU_REG));
1941
+
writel(mask, bank->reg_base + PIC32_SET(CNPU_REG));
1942
1942
break;
1943
1943
case PIN_CONFIG_BIAS_PULL_DOWN:
1944
1944
dev_dbg(pctl->dev, " pulldown\n");
···
1987
1987
.owner = THIS_MODULE,
1988
1988
};
1989
1989
1990
-
static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1990
+
static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1991
1991
{
1992
1992
struct pic32_gpio_bank *bank = gpiochip_get_data(chip);
1993
1993
···
2174
2174
if (IS_ERR(pctl->reg_base))
2175
2175
return PTR_ERR(pctl->reg_base);
2176
2176
2177
-
pctl->clk = devm_clk_get(&pdev->dev, NULL);
2177
+
pctl->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2178
2178
if (IS_ERR(pctl->clk)) {
2179
2179
ret = PTR_ERR(pctl->clk);
2180
-
dev_err(&pdev->dev, "clk get failed\n");
2181
-
return ret;
2182
-
}
2183
-
2184
-
ret = clk_prepare_enable(pctl->clk);
2185
-
if (ret) {
2186
-
dev_err(&pdev->dev, "clk enable failed\n");
2180
+
dev_err(&pdev->dev, "Failed to get and enable clock\n");
2187
2181
return ret;
2188
2182
}
2189
2183
···
2233
2239
if (irq < 0)
2234
2240
return irq;
2235
2241
2236
-
bank->clk = devm_clk_get(&pdev->dev, NULL);
2242
+
bank->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2237
2243
if (IS_ERR(bank->clk)) {
2238
2244
ret = PTR_ERR(bank->clk);
2239
-
dev_err(&pdev->dev, "clk get failed\n");
2240
-
return ret;
2241
-
}
2242
-
2243
-
ret = clk_prepare_enable(bank->clk);
2244
-
if (ret) {
2245
-
dev_err(&pdev->dev, "clk enable failed\n");
2245
+
dev_err(&pdev->dev, "Failed to get and enable clock\n");
2246
2246
return ret;
2247
2247
}
2248
2248
···
2253
2265
girq->default_type = IRQ_TYPE_NONE;
2254
2266
girq->handler = handle_level_irq;
2255
2267
girq->parents[0] = irq;
2256
-
ret = gpiochip_add_data(&bank->gpio_chip, bank);
2268
+
ret = devm_gpiochip_add_data(&pdev->dev, &bank->gpio_chip, bank);
2257
2269
if (ret < 0) {
2258
2270
dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
2259
2271
id, ret);
+312
-1
drivers/pinctrl/pinctrl-rockchip.c
+312
-1
drivers/pinctrl/pinctrl-rockchip.c
···
467
467
* Hardware access
468
468
*/
469
469
470
+
static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
471
+
{
472
+
.num = 1,
473
+
.pin = 6,
474
+
.reg = 0x10024,
475
+
.bit = 8,
476
+
.mask = 0xf
477
+
}, {
478
+
.num = 1,
479
+
.pin = 7,
480
+
.reg = 0x10024,
481
+
.bit = 12,
482
+
.mask = 0xf
483
+
},
484
+
};
485
+
470
486
static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
471
487
{
472
488
.num = 1,
···
1188
1172
else
1189
1173
regmap = info->regmap_base;
1190
1174
1175
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1176
+
return 0;
1177
+
1191
1178
if (ctrl->type == RK3506) {
1192
1179
if (bank->bank_num == 1)
1193
1180
regmap = info->regmap_ioc1;
···
1316
1297
regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1317
1298
else
1318
1299
regmap = info->regmap_base;
1300
+
1301
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1302
+
return 0;
1319
1303
1320
1304
if (ctrl->type == RK3506) {
1321
1305
if (bank->bank_num == 1)
···
1513
1491
1514
1492
*reg += ((pin_num / pins_per_reg) * 4);
1515
1493
*bit = pin_num % pins_per_reg;
1494
+
1495
+
return 0;
1496
+
}
1497
+
1498
+
#define RV1103B_DRV_BITS_PER_PIN 8
1499
+
#define RV1103B_DRV_PINS_PER_REG 2
1500
+
#define RV1103B_DRV_GPIO0_A_OFFSET 0x40100
1501
+
#define RV1103B_DRV_GPIO0_B_OFFSET 0x50110
1502
+
#define RV1103B_DRV_GPIO1_A01_OFFSET 0x140
1503
+
#define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C
1504
+
#define RV1103B_DRV_GPIO2_OFFSET 0x30180
1505
+
#define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C
1506
+
1507
+
static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1508
+
int pin_num, struct regmap **regmap,
1509
+
int *reg, u8 *bit)
1510
+
{
1511
+
struct rockchip_pinctrl *info = bank->drvdata;
1512
+
int ret = 0;
1513
+
1514
+
*regmap = info->regmap_base;
1515
+
switch (bank->bank_num) {
1516
+
case 0:
1517
+
if (pin_num < 7)
1518
+
*reg = RV1103B_DRV_GPIO0_A_OFFSET;
1519
+
else if (pin_num > 7 && pin_num < 14)
1520
+
*reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
1521
+
else
1522
+
ret = -EINVAL;
1523
+
break;
1524
+
1525
+
case 1:
1526
+
if (pin_num < 6)
1527
+
*reg = RV1103B_DRV_GPIO1_A01_OFFSET;
1528
+
else if (pin_num >= 6 && pin_num < 23)
1529
+
*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1530
+
else if (pin_num >= 24 && pin_num < 30)
1531
+
*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1532
+
else
1533
+
ret = -EINVAL;
1534
+
break;
1535
+
1536
+
case 2:
1537
+
if (pin_num < 12) {
1538
+
*reg = RV1103B_DRV_GPIO2_OFFSET;
1539
+
} else if (pin_num >= 16) {
1540
+
ret = -EINVAL;
1541
+
} else {
1542
+
*reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
1543
+
*bit = 10;
1544
+
1545
+
return 0;
1546
+
}
1547
+
break;
1548
+
1549
+
default:
1550
+
ret = -EINVAL;
1551
+
break;
1552
+
}
1553
+
1554
+
if (ret) {
1555
+
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1556
+
1557
+
return ret;
1558
+
}
1559
+
1560
+
*reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
1561
+
*bit = pin_num % RV1103B_DRV_PINS_PER_REG;
1562
+
*bit *= RV1103B_DRV_BITS_PER_PIN;
1563
+
1564
+
return 0;
1565
+
}
1566
+
1567
+
#define RV1103B_PULL_BITS_PER_PIN 2
1568
+
#define RV1103B_PULL_PINS_PER_REG 8
1569
+
#define RV1103B_PULL_GPIO0_A_OFFSET 0x40200
1570
+
#define RV1103B_PULL_GPIO0_B_OFFSET 0x50204
1571
+
#define RV1103B_PULL_GPIO1_A01_OFFSET 0x210
1572
+
#define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210
1573
+
#define RV1103B_PULL_GPIO2_OFFSET 0x30220
1574
+
#define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C
1575
+
1576
+
static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1577
+
int pin_num, struct regmap **regmap,
1578
+
int *reg, u8 *bit)
1579
+
{
1580
+
struct rockchip_pinctrl *info = bank->drvdata;
1581
+
int ret = 0;
1582
+
1583
+
*regmap = info->regmap_base;
1584
+
switch (bank->bank_num) {
1585
+
case 0:
1586
+
if (pin_num < 7)
1587
+
*reg = RV1103B_PULL_GPIO0_A_OFFSET;
1588
+
else if (pin_num > 7 && pin_num < 14)
1589
+
*reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
1590
+
else
1591
+
ret = -EINVAL;
1592
+
break;
1593
+
1594
+
case 1:
1595
+
if (pin_num < 6)
1596
+
*reg = RV1103B_PULL_GPIO1_A01_OFFSET;
1597
+
else if (pin_num >= 6 && pin_num < 23)
1598
+
*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1599
+
else if (pin_num >= 24 && pin_num < 30)
1600
+
*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1601
+
else
1602
+
ret = -EINVAL;
1603
+
break;
1604
+
1605
+
case 2:
1606
+
if (pin_num < 12) {
1607
+
*reg = RV1103B_PULL_GPIO2_OFFSET;
1608
+
} else if (pin_num >= 16) {
1609
+
ret = -EINVAL;
1610
+
} else {
1611
+
*reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
1612
+
*bit = 13;
1613
+
1614
+
return 0;
1615
+
}
1616
+
break;
1617
+
1618
+
default:
1619
+
ret = -EINVAL;
1620
+
break;
1621
+
}
1622
+
1623
+
if (ret) {
1624
+
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1625
+
1626
+
return ret;
1627
+
}
1628
+
1629
+
*reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
1630
+
*bit = pin_num % RV1103B_PULL_PINS_PER_REG;
1631
+
*bit *= RV1103B_PULL_BITS_PER_PIN;
1632
+
1633
+
return 0;
1634
+
}
1635
+
1636
+
#define RV1103B_SMT_BITS_PER_PIN 1
1637
+
#define RV1103B_SMT_PINS_PER_REG 8
1638
+
#define RV1103B_SMT_GPIO0_A_OFFSET 0x40400
1639
+
#define RV1103B_SMT_GPIO0_B_OFFSET 0x50404
1640
+
#define RV1103B_SMT_GPIO1_A01_OFFSET 0x410
1641
+
#define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410
1642
+
#define RV1103B_SMT_GPIO2_OFFSET 0x30420
1643
+
#define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C
1644
+
1645
+
static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1646
+
int pin_num,
1647
+
struct regmap **regmap,
1648
+
int *reg, u8 *bit)
1649
+
{
1650
+
struct rockchip_pinctrl *info = bank->drvdata;
1651
+
int ret = 0;
1652
+
1653
+
*regmap = info->regmap_base;
1654
+
switch (bank->bank_num) {
1655
+
case 0:
1656
+
if (pin_num < 7)
1657
+
*reg = RV1103B_SMT_GPIO0_A_OFFSET;
1658
+
else if (pin_num > 7 && pin_num < 14)
1659
+
*reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
1660
+
else
1661
+
ret = -EINVAL;
1662
+
break;
1663
+
1664
+
case 1:
1665
+
if (pin_num < 6)
1666
+
*reg = RV1103B_SMT_GPIO1_A01_OFFSET;
1667
+
else if (pin_num >= 6 && pin_num < 23)
1668
+
*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1669
+
else if (pin_num >= 24 && pin_num < 30)
1670
+
*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1671
+
else
1672
+
ret = -EINVAL;
1673
+
break;
1674
+
1675
+
case 2:
1676
+
if (pin_num < 12) {
1677
+
*reg = RV1103B_SMT_GPIO2_OFFSET;
1678
+
} else if (pin_num >= 16) {
1679
+
ret = -EINVAL;
1680
+
} else {
1681
+
*reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
1682
+
*bit = 8;
1683
+
1684
+
return 0;
1685
+
}
1686
+
break;
1687
+
1688
+
default:
1689
+
ret = -EINVAL;
1690
+
break;
1691
+
}
1692
+
1693
+
if (ret) {
1694
+
dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1695
+
1696
+
return ret;
1697
+
}
1698
+
1699
+
*reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
1700
+
*bit = pin_num % RV1103B_SMT_PINS_PER_REG;
1701
+
*bit *= RV1103B_SMT_BITS_PER_PIN;
1516
1702
1517
1703
return 0;
1518
1704
}
···
3212
2982
u8 bit;
3213
2983
int drv_type = bank->drv[pin_num / 8].drv_type;
3214
2984
2985
+
if (ctrl->type == RV1103B && pin_num >= 12)
2986
+
drv_type = DRV_TYPE_IO_LEVEL_2_BIT;
2987
+
3215
2988
ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
3216
2989
if (ret)
3217
2990
return ret;
···
3276
3043
if (ret)
3277
3044
return ret;
3278
3045
3046
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3047
+
data = data >> 10;
3048
+
return data & 0x3;
3049
+
}
3050
+
3279
3051
data >>= bit;
3280
3052
data &= (1 << rmask_bits) - 1;
3281
3053
···
3309
3071
rmask_bits = RK3588_DRV_BITS_PER_PIN;
3310
3072
ret = strength;
3311
3073
goto config;
3312
-
} else if (ctrl->type == RK3506 ||
3074
+
} else if (ctrl->type == RV1103B ||
3075
+
ctrl->type == RK3506 ||
3313
3076
ctrl->type == RK3528 ||
3314
3077
ctrl->type == RK3562 ||
3315
3078
ctrl->type == RK3568) {
···
3421
3182
ret = strength;
3422
3183
}
3423
3184
}
3185
+
3186
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3187
+
rmask_bits = 2;
3188
+
ret = strength;
3189
+
}
3190
+
3424
3191
/* enable the write to the equivalent lower bits */
3425
3192
data = ((1 << rmask_bits) - 1) << (bit + 16);
3426
3193
rmask = data | (data >> 16);
···
3481
3236
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
3482
3237
: PIN_CONFIG_BIAS_DISABLE;
3483
3238
case PX30:
3239
+
case RV1103B:
3484
3240
case RV1108:
3485
3241
case RK3188:
3486
3242
case RK3288:
···
3497
3251
pull_type = bank->pull_type[pin_num / 8];
3498
3252
data >>= bit;
3499
3253
data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
3254
+
3255
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3256
+
pull_type = 1;
3500
3257
/*
3501
3258
* In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3502
3259
* where that pull up value becomes 3.
···
3546
3297
ret = regmap_write(regmap, reg, data);
3547
3298
break;
3548
3299
case PX30:
3300
+
case RV1103B:
3549
3301
case RV1108:
3550
3302
case RV1126:
3551
3303
case RK3188:
···
3562
3312
case RK3576:
3563
3313
case RK3588:
3564
3314
pull_type = bank->pull_type[pin_num / 8];
3315
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3316
+
pull_type = 1;
3565
3317
ret = -EINVAL;
3566
3318
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
3567
3319
i++) {
···
3669
3417
if (ret)
3670
3418
return ret;
3671
3419
3420
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3421
+
data >>= 8;
3422
+
return data & 0x3;
3423
+
}
3424
+
3672
3425
data >>= bit;
3673
3426
switch (ctrl->type) {
3674
3427
case RK3562:
···
3728
3471
rmask = data | (data >> 16);
3729
3472
data |= ((enable ? 0x3 : 0) << bit);
3730
3473
}
3474
+
}
3475
+
3476
+
if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3477
+
data = 0x3 << (bit + 16);
3478
+
rmask = data | (data >> 16);
3479
+
data |= ((enable ? 0x3 : 0) << bit);
3731
3480
}
3732
3481
3733
3482
return regmap_update_bits(regmap, reg, rmask, data);
···
3842
3579
case RK3066B:
3843
3580
return pull ? false : true;
3844
3581
case PX30:
3582
+
case RV1103B:
3845
3583
case RV1108:
3846
3584
case RV1126:
3847
3585
case RK3188:
···
4578
4314
.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
4579
4315
};
4580
4316
4317
+
static struct rockchip_pin_bank rv1103b_pin_banks[] = {
4318
+
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
4319
+
IOMUX_WIDTH_4BIT,
4320
+
IOMUX_WIDTH_4BIT,
4321
+
IOMUX_WIDTH_4BIT,
4322
+
IOMUX_WIDTH_4BIT,
4323
+
0x40000, 0x50008, 0x50010, 0x50018,
4324
+
DRV_TYPE_IO_LEVEL_8_BIT,
4325
+
DRV_TYPE_IO_LEVEL_8_BIT,
4326
+
DRV_TYPE_IO_LEVEL_8_BIT,
4327
+
DRV_TYPE_IO_LEVEL_8_BIT),
4328
+
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
4329
+
IOMUX_WIDTH_4BIT,
4330
+
IOMUX_WIDTH_4BIT,
4331
+
IOMUX_WIDTH_4BIT,
4332
+
IOMUX_WIDTH_4BIT,
4333
+
0x20, 0x10028, 0x10030, 0x10038,
4334
+
DRV_TYPE_IO_LEVEL_8_BIT,
4335
+
DRV_TYPE_IO_LEVEL_8_BIT,
4336
+
DRV_TYPE_IO_LEVEL_8_BIT,
4337
+
DRV_TYPE_IO_LEVEL_8_BIT),
4338
+
PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
4339
+
IOMUX_WIDTH_4BIT,
4340
+
IOMUX_WIDTH_4BIT,
4341
+
IOMUX_WIDTH_4BIT,
4342
+
IOMUX_WIDTH_4BIT,
4343
+
0x30040, 0x30048, 0x30050, 0x30058,
4344
+
DRV_TYPE_IO_LEVEL_8_BIT,
4345
+
DRV_TYPE_IO_LEVEL_8_BIT,
4346
+
DRV_TYPE_IO_LEVEL_8_BIT,
4347
+
DRV_TYPE_IO_LEVEL_8_BIT),
4348
+
};
4349
+
4350
+
static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
4351
+
.pin_banks = rv1103b_pin_banks,
4352
+
.nr_banks = ARRAY_SIZE(rv1103b_pin_banks),
4353
+
.label = "RV1103B-GPIO",
4354
+
.type = RV1103B,
4355
+
.iomux_recalced = rv1103b_mux_recalced_data,
4356
+
.niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data),
4357
+
.pull_calc_reg = rv1103b_calc_pull_reg_and_bit,
4358
+
.drv_calc_reg = rv1103b_calc_drv_reg_and_bit,
4359
+
.schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit,
4360
+
};
4361
+
4581
4362
static struct rockchip_pin_bank rv1108_pin_banks[] = {
4582
4363
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4583
4364
IOMUX_SOURCE_PMU,
···
5259
4950
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
5260
4951
{ .compatible = "rockchip,px30-pinctrl",
5261
4952
.data = &px30_pin_ctrl },
4953
+
{ .compatible = "rockchip,rv1103b-pinctrl",
4954
+
.data = &rv1103b_pin_ctrl },
5262
4955
{ .compatible = "rockchip,rv1108-pinctrl",
5263
4956
.data = &rv1108_pin_ctrl },
5264
4957
{ .compatible = "rockchip,rv1126-pinctrl",
+1
drivers/pinctrl/pinctrl-rockchip.h
+1
drivers/pinctrl/pinctrl-rockchip.h
+4
-2
drivers/pinctrl/pinctrl-single.c
+4
-2
drivers/pinctrl/pinctrl-single.c
···
1960
1960
.irq_status_mask = (1 << 30), /* WKUP_EVT */
1961
1961
};
1962
1962
1963
-
static const struct pcs_soc_data pinctrl_single_j7200 = {
1963
+
static const struct pcs_soc_data pinctrl_single_loss_off = {
1964
1964
.flags = PCS_CONTEXT_LOSS_OFF,
1965
1965
};
1966
1966
···
1972
1972
};
1973
1973
1974
1974
static const struct of_device_id pcs_of_match[] = {
1975
+
{ .compatible = "brcm,bcm7038-padconf", .data = &pinctrl_single_loss_off },
1975
1976
{ .compatible = "marvell,pxa1908-padconf", .data = &pinconf_single },
1976
1977
{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1977
1978
{ .compatible = "ti,am654-padconf", .data = &pinctrl_single_am654 },
···
1980
1979
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1981
1980
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1982
1981
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1983
-
{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_j7200 },
1982
+
{ .compatible = "ti,j7200-padconf", .data = &pinctrl_single_loss_off },
1983
+
{ .compatible = "ti,am62l-padconf", .data = &pinctrl_single_loss_off },
1984
1984
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
1985
1985
{ .compatible = "pinconf-single", .data = &pinconf_single },
1986
1986
{ },
+20
drivers/pinctrl/qcom/Kconfig
+20
drivers/pinctrl/qcom/Kconfig
···
60
60
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
61
61
(Low Power Island) found on the Qualcomm Technologies Inc SoCs.
62
62
63
+
config PINCTRL_MILOS_LPASS_LPI
64
+
tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver"
65
+
depends on ARM64 || COMPILE_TEST
66
+
depends on PINCTRL_LPASS_LPI
67
+
help
68
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69
+
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
70
+
(Low Power Island) found on the Qualcomm Technologies Inc Milos
71
+
platform.
72
+
63
73
config PINCTRL_SC7280_LPASS_LPI
64
74
tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin controller driver"
65
75
depends on ARM64 || COMPILE_TEST
···
98
88
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
99
89
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
100
90
(Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
91
+
92
+
config PINCTRL_SDM670_LPASS_LPI
93
+
tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver"
94
+
depends on GPIOLIB
95
+
depends on ARM64 || COMPILE_TEST
96
+
depends on PINCTRL_LPASS_LPI
97
+
help
98
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
99
+
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
100
+
(Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.
101
101
102
102
config PINCTRL_SM6115_LPASS_LPI
103
103
tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
+28
drivers/pinctrl/qcom/Kconfig.msm
+28
drivers/pinctrl/qcom/Kconfig.msm
···
15
15
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16
16
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
17
17
18
+
config PINCTRL_ELIZA
19
+
tristate "Qualcomm Technologies Inc Eliza pin controller driver"
20
+
depends on ARM64 || COMPILE_TEST
21
+
help
22
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
23
+
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
24
+
block found on the Qualcomm Technologies Inc Eliza platform.
25
+
Say Y here to compile statically, or M here to compile it as a module.
26
+
If unsure, say N.
27
+
18
28
config PINCTRL_GLYMUR
19
29
tristate "Qualcomm Technologies Inc Glymur pin controller driver"
20
30
depends on ARM64 || COMPILE_TEST
···
32
22
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
33
23
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
34
24
block found on the Qualcomm Technologies Inc Glymur platform.
25
+
Say Y here to compile statically, or M here to compile it as a module.
26
+
If unsure, say N.
27
+
28
+
config PINCTRL_HAWI
29
+
tristate "Qualcomm Technologies Inc Hawi pin controller driver"
30
+
depends on ARM64 || COMPILE_TEST
31
+
help
32
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
33
+
Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM)
34
+
block found on the Qualcomm Technologies Inc Hawi platform.
35
35
Say Y here to compile statically, or M here to compile it as a module.
36
36
If unsure, say N.
37
37
···
67
47
help
68
48
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
69
49
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
50
+
51
+
config PINCTRL_IPQ5210
52
+
tristate "Qualcomm Technologies Inc IPQ5210 pin controller driver"
53
+
depends on ARM64 || COMPILE_TEST
54
+
help
55
+
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
56
+
Qualcomm Technologies Inc TLMM block found on the Qualcomm
57
+
Technologies Inc IPQ5210 platform.
70
58
71
59
config PINCTRL_IPQ5332
72
60
tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
+5
drivers/pinctrl/qcom/Makefile
+5
drivers/pinctrl/qcom/Makefile
···
3
3
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
4
4
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
5
5
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
6
+
obj-$(CONFIG_PINCTRL_ELIZA) += pinctrl-eliza.o
6
7
obj-$(CONFIG_PINCTRL_GLYMUR) += pinctrl-glymur.o
8
+
obj-$(CONFIG_PINCTRL_HAWI) += pinctrl-hawi.o
7
9
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
8
10
obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
9
11
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
12
+
obj-$(CONFIG_PINCTRL_IPQ5210) += pinctrl-ipq5210.o
10
13
obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
11
14
obj-$(CONFIG_PINCTRL_IPQ5424) += pinctrl-ipq5424.o
12
15
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
···
36
33
obj-$(CONFIG_PINCTRL_MDM9607) += pinctrl-mdm9607.o
37
34
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
38
35
obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o
36
+
obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o
39
37
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
40
38
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
41
39
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
···
52
48
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
53
49
obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o
54
50
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
51
+
obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o
55
52
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
56
53
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
57
54
obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
-2
drivers/pinctrl/qcom/pinctrl-apq8084.c
-2
drivers/pinctrl/qcom/pinctrl-apq8084.c
···
343
343
.io_reg = 0x1004 + 0x10 * id, \
344
344
.intr_cfg_reg = 0x1008 + 0x10 * id, \
345
345
.intr_status_reg = 0x100c + 0x10 * id, \
346
-
.intr_target_reg = 0x1008 + 0x10 * id, \
347
346
.mux_bit = 2, \
348
347
.pull_bit = 0, \
349
348
.drv_bit = 6, \
···
369
370
.io_reg = 0, \
370
371
.intr_cfg_reg = 0, \
371
372
.intr_status_reg = 0, \
372
-
.intr_target_reg = 0, \
373
373
.mux_bit = -1, \
374
374
.pull_bit = pull, \
375
375
.drv_bit = drv, \
+1545
drivers/pinctrl/qcom/pinctrl-eliza.c
+1545
drivers/pinctrl/qcom/pinctrl-eliza.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
14
+
{ \
15
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
16
+
gpio##id##_pins, \
17
+
ARRAY_SIZE(gpio##id##_pins)), \
18
+
.funcs = (int[]){ \
19
+
msm_mux_gpio, /* gpio mode */ \
20
+
msm_mux_##f1, \
21
+
msm_mux_##f2, \
22
+
msm_mux_##f3, \
23
+
msm_mux_##f4, \
24
+
msm_mux_##f5, \
25
+
msm_mux_##f6, \
26
+
msm_mux_##f7, \
27
+
msm_mux_##f8, \
28
+
msm_mux_##f9, \
29
+
msm_mux_##f10, \
30
+
msm_mux_##f11 /* egpio mode */ \
31
+
}, \
32
+
.nfuncs = 12, \
33
+
.ctl_reg = REG_SIZE * id, \
34
+
.io_reg = 0x4 + REG_SIZE * id, \
35
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
+
.intr_status_reg = 0xc + REG_SIZE * id, \
37
+
.mux_bit = 2, \
38
+
.pull_bit = 0, \
39
+
.drv_bit = 6, \
40
+
.egpio_enable = 12, \
41
+
.egpio_present = 11, \
42
+
.oe_bit = 9, \
43
+
.in_bit = 0, \
44
+
.out_bit = 1, \
45
+
.intr_enable_bit = 0, \
46
+
.intr_status_bit = 0, \
47
+
.intr_wakeup_present_bit = 6, \
48
+
.intr_wakeup_enable_bit = 7, \
49
+
.intr_target_bit = 8, \
50
+
.intr_target_kpss_val = 3, \
51
+
.intr_raw_status_bit = 4, \
52
+
.intr_polarity_bit = 1, \
53
+
.intr_detection_bit = 2, \
54
+
.intr_detection_width = 2, \
55
+
}
56
+
57
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
58
+
{ \
59
+
.grp = PINCTRL_PINGROUP(#pg_name, \
60
+
pg_name##_pins, \
61
+
ARRAY_SIZE(pg_name##_pins)), \
62
+
.ctl_reg = ctl, \
63
+
.io_reg = 0, \
64
+
.intr_cfg_reg = 0, \
65
+
.intr_status_reg = 0, \
66
+
.mux_bit = -1, \
67
+
.pull_bit = pull, \
68
+
.drv_bit = drv, \
69
+
.oe_bit = -1, \
70
+
.in_bit = -1, \
71
+
.out_bit = -1, \
72
+
.intr_enable_bit = -1, \
73
+
.intr_status_bit = -1, \
74
+
.intr_target_bit = -1, \
75
+
.intr_raw_status_bit = -1, \
76
+
.intr_polarity_bit = -1, \
77
+
.intr_detection_bit = -1, \
78
+
.intr_detection_width = -1, \
79
+
}
80
+
81
+
#define UFS_RESET(pg_name, ctl, io) \
82
+
{ \
83
+
.grp = PINCTRL_PINGROUP(#pg_name, \
84
+
pg_name##_pins, \
85
+
ARRAY_SIZE(pg_name##_pins)), \
86
+
.ctl_reg = ctl, \
87
+
.io_reg = io, \
88
+
.intr_cfg_reg = 0, \
89
+
.intr_status_reg = 0, \
90
+
.mux_bit = -1, \
91
+
.pull_bit = 3, \
92
+
.drv_bit = 0, \
93
+
.oe_bit = -1, \
94
+
.in_bit = -1, \
95
+
.out_bit = 0, \
96
+
.intr_enable_bit = -1, \
97
+
.intr_status_bit = -1, \
98
+
.intr_target_bit = -1, \
99
+
.intr_raw_status_bit = -1, \
100
+
.intr_polarity_bit = -1, \
101
+
.intr_detection_bit = -1, \
102
+
.intr_detection_width = -1, \
103
+
}
104
+
105
+
static const struct pinctrl_pin_desc eliza_pins[] = {
106
+
PINCTRL_PIN(0, "GPIO_0"),
107
+
PINCTRL_PIN(1, "GPIO_1"),
108
+
PINCTRL_PIN(2, "GPIO_2"),
109
+
PINCTRL_PIN(3, "GPIO_3"),
110
+
PINCTRL_PIN(4, "GPIO_4"),
111
+
PINCTRL_PIN(5, "GPIO_5"),
112
+
PINCTRL_PIN(6, "GPIO_6"),
113
+
PINCTRL_PIN(7, "GPIO_7"),
114
+
PINCTRL_PIN(8, "GPIO_8"),
115
+
PINCTRL_PIN(9, "GPIO_9"),
116
+
PINCTRL_PIN(10, "GPIO_10"),
117
+
PINCTRL_PIN(11, "GPIO_11"),
118
+
PINCTRL_PIN(12, "GPIO_12"),
119
+
PINCTRL_PIN(13, "GPIO_13"),
120
+
PINCTRL_PIN(14, "GPIO_14"),
121
+
PINCTRL_PIN(15, "GPIO_15"),
122
+
PINCTRL_PIN(16, "GPIO_16"),
123
+
PINCTRL_PIN(17, "GPIO_17"),
124
+
PINCTRL_PIN(18, "GPIO_18"),
125
+
PINCTRL_PIN(19, "GPIO_19"),
126
+
PINCTRL_PIN(20, "GPIO_20"),
127
+
PINCTRL_PIN(21, "GPIO_21"),
128
+
PINCTRL_PIN(22, "GPIO_22"),
129
+
PINCTRL_PIN(23, "GPIO_23"),
130
+
PINCTRL_PIN(24, "GPIO_24"),
131
+
PINCTRL_PIN(25, "GPIO_25"),
132
+
PINCTRL_PIN(26, "GPIO_26"),
133
+
PINCTRL_PIN(27, "GPIO_27"),
134
+
PINCTRL_PIN(28, "GPIO_28"),
135
+
PINCTRL_PIN(29, "GPIO_29"),
136
+
PINCTRL_PIN(30, "GPIO_30"),
137
+
PINCTRL_PIN(31, "GPIO_31"),
138
+
PINCTRL_PIN(32, "GPIO_32"),
139
+
PINCTRL_PIN(33, "GPIO_33"),
140
+
PINCTRL_PIN(34, "GPIO_34"),
141
+
PINCTRL_PIN(35, "GPIO_35"),
142
+
PINCTRL_PIN(36, "GPIO_36"),
143
+
PINCTRL_PIN(37, "GPIO_37"),
144
+
PINCTRL_PIN(38, "GPIO_38"),
145
+
PINCTRL_PIN(39, "GPIO_39"),
146
+
PINCTRL_PIN(40, "GPIO_40"),
147
+
PINCTRL_PIN(41, "GPIO_41"),
148
+
PINCTRL_PIN(42, "GPIO_42"),
149
+
PINCTRL_PIN(43, "GPIO_43"),
150
+
PINCTRL_PIN(44, "GPIO_44"),
151
+
PINCTRL_PIN(45, "GPIO_45"),
152
+
PINCTRL_PIN(46, "GPIO_46"),
153
+
PINCTRL_PIN(47, "GPIO_47"),
154
+
PINCTRL_PIN(48, "GPIO_48"),
155
+
PINCTRL_PIN(49, "GPIO_49"),
156
+
PINCTRL_PIN(50, "GPIO_50"),
157
+
PINCTRL_PIN(51, "GPIO_51"),
158
+
PINCTRL_PIN(52, "GPIO_52"),
159
+
PINCTRL_PIN(53, "GPIO_53"),
160
+
PINCTRL_PIN(54, "GPIO_54"),
161
+
PINCTRL_PIN(55, "GPIO_55"),
162
+
PINCTRL_PIN(56, "GPIO_56"),
163
+
PINCTRL_PIN(57, "GPIO_57"),
164
+
PINCTRL_PIN(58, "GPIO_58"),
165
+
PINCTRL_PIN(59, "GPIO_59"),
166
+
PINCTRL_PIN(60, "GPIO_60"),
167
+
PINCTRL_PIN(61, "GPIO_61"),
168
+
PINCTRL_PIN(62, "GPIO_62"),
169
+
PINCTRL_PIN(63, "GPIO_63"),
170
+
PINCTRL_PIN(64, "GPIO_64"),
171
+
PINCTRL_PIN(65, "GPIO_65"),
172
+
PINCTRL_PIN(66, "GPIO_66"),
173
+
PINCTRL_PIN(67, "GPIO_67"),
174
+
PINCTRL_PIN(68, "GPIO_68"),
175
+
PINCTRL_PIN(69, "GPIO_69"),
176
+
PINCTRL_PIN(70, "GPIO_70"),
177
+
PINCTRL_PIN(71, "GPIO_71"),
178
+
PINCTRL_PIN(72, "GPIO_72"),
179
+
PINCTRL_PIN(73, "GPIO_73"),
180
+
PINCTRL_PIN(74, "GPIO_74"),
181
+
PINCTRL_PIN(75, "GPIO_75"),
182
+
PINCTRL_PIN(76, "GPIO_76"),
183
+
PINCTRL_PIN(77, "GPIO_77"),
184
+
PINCTRL_PIN(78, "GPIO_78"),
185
+
PINCTRL_PIN(79, "GPIO_79"),
186
+
PINCTRL_PIN(80, "GPIO_80"),
187
+
PINCTRL_PIN(81, "GPIO_81"),
188
+
PINCTRL_PIN(82, "GPIO_82"),
189
+
PINCTRL_PIN(83, "GPIO_83"),
190
+
PINCTRL_PIN(84, "GPIO_84"),
191
+
PINCTRL_PIN(85, "GPIO_85"),
192
+
PINCTRL_PIN(86, "GPIO_86"),
193
+
PINCTRL_PIN(87, "GPIO_87"),
194
+
PINCTRL_PIN(88, "GPIO_88"),
195
+
PINCTRL_PIN(89, "GPIO_89"),
196
+
PINCTRL_PIN(90, "GPIO_90"),
197
+
PINCTRL_PIN(91, "GPIO_91"),
198
+
PINCTRL_PIN(92, "GPIO_92"),
199
+
PINCTRL_PIN(93, "GPIO_93"),
200
+
PINCTRL_PIN(94, "GPIO_94"),
201
+
PINCTRL_PIN(95, "GPIO_95"),
202
+
PINCTRL_PIN(96, "GPIO_96"),
203
+
PINCTRL_PIN(97, "GPIO_97"),
204
+
PINCTRL_PIN(98, "GPIO_98"),
205
+
PINCTRL_PIN(99, "GPIO_99"),
206
+
PINCTRL_PIN(100, "GPIO_100"),
207
+
PINCTRL_PIN(101, "GPIO_101"),
208
+
PINCTRL_PIN(102, "GPIO_102"),
209
+
PINCTRL_PIN(103, "GPIO_103"),
210
+
PINCTRL_PIN(104, "GPIO_104"),
211
+
PINCTRL_PIN(105, "GPIO_105"),
212
+
PINCTRL_PIN(106, "GPIO_106"),
213
+
PINCTRL_PIN(107, "GPIO_107"),
214
+
PINCTRL_PIN(108, "GPIO_108"),
215
+
PINCTRL_PIN(109, "GPIO_109"),
216
+
PINCTRL_PIN(110, "GPIO_110"),
217
+
PINCTRL_PIN(111, "GPIO_111"),
218
+
PINCTRL_PIN(112, "GPIO_112"),
219
+
PINCTRL_PIN(113, "GPIO_113"),
220
+
PINCTRL_PIN(114, "GPIO_114"),
221
+
PINCTRL_PIN(115, "GPIO_115"),
222
+
PINCTRL_PIN(116, "GPIO_116"),
223
+
PINCTRL_PIN(117, "GPIO_117"),
224
+
PINCTRL_PIN(118, "GPIO_118"),
225
+
PINCTRL_PIN(119, "GPIO_119"),
226
+
PINCTRL_PIN(120, "GPIO_120"),
227
+
PINCTRL_PIN(121, "GPIO_121"),
228
+
PINCTRL_PIN(122, "GPIO_122"),
229
+
PINCTRL_PIN(123, "GPIO_123"),
230
+
PINCTRL_PIN(124, "GPIO_124"),
231
+
PINCTRL_PIN(125, "GPIO_125"),
232
+
PINCTRL_PIN(126, "GPIO_126"),
233
+
PINCTRL_PIN(127, "GPIO_127"),
234
+
PINCTRL_PIN(128, "GPIO_128"),
235
+
PINCTRL_PIN(129, "GPIO_129"),
236
+
PINCTRL_PIN(130, "GPIO_130"),
237
+
PINCTRL_PIN(131, "GPIO_131"),
238
+
PINCTRL_PIN(132, "GPIO_132"),
239
+
PINCTRL_PIN(133, "GPIO_133"),
240
+
PINCTRL_PIN(134, "GPIO_134"),
241
+
PINCTRL_PIN(135, "GPIO_135"),
242
+
PINCTRL_PIN(136, "GPIO_136"),
243
+
PINCTRL_PIN(137, "GPIO_137"),
244
+
PINCTRL_PIN(138, "GPIO_138"),
245
+
PINCTRL_PIN(139, "GPIO_139"),
246
+
PINCTRL_PIN(140, "GPIO_140"),
247
+
PINCTRL_PIN(141, "GPIO_141"),
248
+
PINCTRL_PIN(142, "GPIO_142"),
249
+
PINCTRL_PIN(143, "GPIO_143"),
250
+
PINCTRL_PIN(144, "GPIO_144"),
251
+
PINCTRL_PIN(145, "GPIO_145"),
252
+
PINCTRL_PIN(146, "GPIO_146"),
253
+
PINCTRL_PIN(147, "GPIO_147"),
254
+
PINCTRL_PIN(148, "GPIO_148"),
255
+
PINCTRL_PIN(149, "GPIO_149"),
256
+
PINCTRL_PIN(150, "GPIO_150"),
257
+
PINCTRL_PIN(151, "GPIO_151"),
258
+
PINCTRL_PIN(152, "GPIO_152"),
259
+
PINCTRL_PIN(153, "GPIO_153"),
260
+
PINCTRL_PIN(154, "GPIO_154"),
261
+
PINCTRL_PIN(155, "GPIO_155"),
262
+
PINCTRL_PIN(156, "GPIO_156"),
263
+
PINCTRL_PIN(157, "GPIO_157"),
264
+
PINCTRL_PIN(158, "GPIO_158"),
265
+
PINCTRL_PIN(159, "GPIO_159"),
266
+
PINCTRL_PIN(160, "GPIO_160"),
267
+
PINCTRL_PIN(161, "GPIO_161"),
268
+
PINCTRL_PIN(162, "GPIO_162"),
269
+
PINCTRL_PIN(163, "GPIO_163"),
270
+
PINCTRL_PIN(164, "GPIO_164"),
271
+
PINCTRL_PIN(165, "GPIO_165"),
272
+
PINCTRL_PIN(166, "GPIO_166"),
273
+
PINCTRL_PIN(167, "GPIO_167"),
274
+
PINCTRL_PIN(168, "GPIO_168"),
275
+
PINCTRL_PIN(169, "GPIO_169"),
276
+
PINCTRL_PIN(170, "GPIO_170"),
277
+
PINCTRL_PIN(171, "GPIO_171"),
278
+
PINCTRL_PIN(172, "GPIO_172"),
279
+
PINCTRL_PIN(173, "GPIO_173"),
280
+
PINCTRL_PIN(174, "GPIO_174"),
281
+
PINCTRL_PIN(175, "GPIO_175"),
282
+
PINCTRL_PIN(176, "GPIO_176"),
283
+
PINCTRL_PIN(177, "GPIO_177"),
284
+
PINCTRL_PIN(178, "GPIO_178"),
285
+
PINCTRL_PIN(179, "GPIO_179"),
286
+
PINCTRL_PIN(180, "GPIO_180"),
287
+
PINCTRL_PIN(181, "GPIO_181"),
288
+
PINCTRL_PIN(182, "GPIO_182"),
289
+
PINCTRL_PIN(183, "GPIO_183"),
290
+
PINCTRL_PIN(184, "GPIO_184"),
291
+
PINCTRL_PIN(185, "UFS_RESET"),
292
+
};
293
+
294
+
#define DECLARE_MSM_GPIO_PINS(pin) \
295
+
static const unsigned int gpio##pin##_pins[] = { pin }
296
+
DECLARE_MSM_GPIO_PINS(0);
297
+
DECLARE_MSM_GPIO_PINS(1);
298
+
DECLARE_MSM_GPIO_PINS(2);
299
+
DECLARE_MSM_GPIO_PINS(3);
300
+
DECLARE_MSM_GPIO_PINS(4);
301
+
DECLARE_MSM_GPIO_PINS(5);
302
+
DECLARE_MSM_GPIO_PINS(6);
303
+
DECLARE_MSM_GPIO_PINS(7);
304
+
DECLARE_MSM_GPIO_PINS(8);
305
+
DECLARE_MSM_GPIO_PINS(9);
306
+
DECLARE_MSM_GPIO_PINS(10);
307
+
DECLARE_MSM_GPIO_PINS(11);
308
+
DECLARE_MSM_GPIO_PINS(12);
309
+
DECLARE_MSM_GPIO_PINS(13);
310
+
DECLARE_MSM_GPIO_PINS(14);
311
+
DECLARE_MSM_GPIO_PINS(15);
312
+
DECLARE_MSM_GPIO_PINS(16);
313
+
DECLARE_MSM_GPIO_PINS(17);
314
+
DECLARE_MSM_GPIO_PINS(18);
315
+
DECLARE_MSM_GPIO_PINS(19);
316
+
DECLARE_MSM_GPIO_PINS(20);
317
+
DECLARE_MSM_GPIO_PINS(21);
318
+
DECLARE_MSM_GPIO_PINS(22);
319
+
DECLARE_MSM_GPIO_PINS(23);
320
+
DECLARE_MSM_GPIO_PINS(24);
321
+
DECLARE_MSM_GPIO_PINS(25);
322
+
DECLARE_MSM_GPIO_PINS(26);
323
+
DECLARE_MSM_GPIO_PINS(27);
324
+
DECLARE_MSM_GPIO_PINS(28);
325
+
DECLARE_MSM_GPIO_PINS(29);
326
+
DECLARE_MSM_GPIO_PINS(30);
327
+
DECLARE_MSM_GPIO_PINS(31);
328
+
DECLARE_MSM_GPIO_PINS(32);
329
+
DECLARE_MSM_GPIO_PINS(33);
330
+
DECLARE_MSM_GPIO_PINS(34);
331
+
DECLARE_MSM_GPIO_PINS(35);
332
+
DECLARE_MSM_GPIO_PINS(36);
333
+
DECLARE_MSM_GPIO_PINS(37);
334
+
DECLARE_MSM_GPIO_PINS(38);
335
+
DECLARE_MSM_GPIO_PINS(39);
336
+
DECLARE_MSM_GPIO_PINS(40);
337
+
DECLARE_MSM_GPIO_PINS(41);
338
+
DECLARE_MSM_GPIO_PINS(42);
339
+
DECLARE_MSM_GPIO_PINS(43);
340
+
DECLARE_MSM_GPIO_PINS(44);
341
+
DECLARE_MSM_GPIO_PINS(45);
342
+
DECLARE_MSM_GPIO_PINS(46);
343
+
DECLARE_MSM_GPIO_PINS(47);
344
+
DECLARE_MSM_GPIO_PINS(48);
345
+
DECLARE_MSM_GPIO_PINS(49);
346
+
DECLARE_MSM_GPIO_PINS(50);
347
+
DECLARE_MSM_GPIO_PINS(51);
348
+
DECLARE_MSM_GPIO_PINS(52);
349
+
DECLARE_MSM_GPIO_PINS(53);
350
+
DECLARE_MSM_GPIO_PINS(54);
351
+
DECLARE_MSM_GPIO_PINS(55);
352
+
DECLARE_MSM_GPIO_PINS(56);
353
+
DECLARE_MSM_GPIO_PINS(57);
354
+
DECLARE_MSM_GPIO_PINS(58);
355
+
DECLARE_MSM_GPIO_PINS(59);
356
+
DECLARE_MSM_GPIO_PINS(60);
357
+
DECLARE_MSM_GPIO_PINS(61);
358
+
DECLARE_MSM_GPIO_PINS(62);
359
+
DECLARE_MSM_GPIO_PINS(63);
360
+
DECLARE_MSM_GPIO_PINS(64);
361
+
DECLARE_MSM_GPIO_PINS(65);
362
+
DECLARE_MSM_GPIO_PINS(66);
363
+
DECLARE_MSM_GPIO_PINS(67);
364
+
DECLARE_MSM_GPIO_PINS(68);
365
+
DECLARE_MSM_GPIO_PINS(69);
366
+
DECLARE_MSM_GPIO_PINS(70);
367
+
DECLARE_MSM_GPIO_PINS(71);
368
+
DECLARE_MSM_GPIO_PINS(72);
369
+
DECLARE_MSM_GPIO_PINS(73);
370
+
DECLARE_MSM_GPIO_PINS(74);
371
+
DECLARE_MSM_GPIO_PINS(75);
372
+
DECLARE_MSM_GPIO_PINS(76);
373
+
DECLARE_MSM_GPIO_PINS(77);
374
+
DECLARE_MSM_GPIO_PINS(78);
375
+
DECLARE_MSM_GPIO_PINS(79);
376
+
DECLARE_MSM_GPIO_PINS(80);
377
+
DECLARE_MSM_GPIO_PINS(81);
378
+
DECLARE_MSM_GPIO_PINS(82);
379
+
DECLARE_MSM_GPIO_PINS(83);
380
+
DECLARE_MSM_GPIO_PINS(84);
381
+
DECLARE_MSM_GPIO_PINS(85);
382
+
DECLARE_MSM_GPIO_PINS(86);
383
+
DECLARE_MSM_GPIO_PINS(87);
384
+
DECLARE_MSM_GPIO_PINS(88);
385
+
DECLARE_MSM_GPIO_PINS(89);
386
+
DECLARE_MSM_GPIO_PINS(90);
387
+
DECLARE_MSM_GPIO_PINS(91);
388
+
DECLARE_MSM_GPIO_PINS(92);
389
+
DECLARE_MSM_GPIO_PINS(93);
390
+
DECLARE_MSM_GPIO_PINS(94);
391
+
DECLARE_MSM_GPIO_PINS(95);
392
+
DECLARE_MSM_GPIO_PINS(96);
393
+
DECLARE_MSM_GPIO_PINS(97);
394
+
DECLARE_MSM_GPIO_PINS(98);
395
+
DECLARE_MSM_GPIO_PINS(99);
396
+
DECLARE_MSM_GPIO_PINS(100);
397
+
DECLARE_MSM_GPIO_PINS(101);
398
+
DECLARE_MSM_GPIO_PINS(102);
399
+
DECLARE_MSM_GPIO_PINS(103);
400
+
DECLARE_MSM_GPIO_PINS(104);
401
+
DECLARE_MSM_GPIO_PINS(105);
402
+
DECLARE_MSM_GPIO_PINS(106);
403
+
DECLARE_MSM_GPIO_PINS(107);
404
+
DECLARE_MSM_GPIO_PINS(108);
405
+
DECLARE_MSM_GPIO_PINS(109);
406
+
DECLARE_MSM_GPIO_PINS(110);
407
+
DECLARE_MSM_GPIO_PINS(111);
408
+
DECLARE_MSM_GPIO_PINS(112);
409
+
DECLARE_MSM_GPIO_PINS(113);
410
+
DECLARE_MSM_GPIO_PINS(114);
411
+
DECLARE_MSM_GPIO_PINS(115);
412
+
DECLARE_MSM_GPIO_PINS(116);
413
+
DECLARE_MSM_GPIO_PINS(117);
414
+
DECLARE_MSM_GPIO_PINS(118);
415
+
DECLARE_MSM_GPIO_PINS(119);
416
+
DECLARE_MSM_GPIO_PINS(120);
417
+
DECLARE_MSM_GPIO_PINS(121);
418
+
DECLARE_MSM_GPIO_PINS(122);
419
+
DECLARE_MSM_GPIO_PINS(123);
420
+
DECLARE_MSM_GPIO_PINS(124);
421
+
DECLARE_MSM_GPIO_PINS(125);
422
+
DECLARE_MSM_GPIO_PINS(126);
423
+
DECLARE_MSM_GPIO_PINS(127);
424
+
DECLARE_MSM_GPIO_PINS(128);
425
+
DECLARE_MSM_GPIO_PINS(129);
426
+
DECLARE_MSM_GPIO_PINS(130);
427
+
DECLARE_MSM_GPIO_PINS(131);
428
+
DECLARE_MSM_GPIO_PINS(132);
429
+
DECLARE_MSM_GPIO_PINS(133);
430
+
DECLARE_MSM_GPIO_PINS(134);
431
+
DECLARE_MSM_GPIO_PINS(135);
432
+
DECLARE_MSM_GPIO_PINS(136);
433
+
DECLARE_MSM_GPIO_PINS(137);
434
+
DECLARE_MSM_GPIO_PINS(138);
435
+
DECLARE_MSM_GPIO_PINS(139);
436
+
DECLARE_MSM_GPIO_PINS(140);
437
+
DECLARE_MSM_GPIO_PINS(141);
438
+
DECLARE_MSM_GPIO_PINS(142);
439
+
DECLARE_MSM_GPIO_PINS(143);
440
+
DECLARE_MSM_GPIO_PINS(144);
441
+
DECLARE_MSM_GPIO_PINS(145);
442
+
DECLARE_MSM_GPIO_PINS(146);
443
+
DECLARE_MSM_GPIO_PINS(147);
444
+
DECLARE_MSM_GPIO_PINS(148);
445
+
DECLARE_MSM_GPIO_PINS(149);
446
+
DECLARE_MSM_GPIO_PINS(150);
447
+
DECLARE_MSM_GPIO_PINS(151);
448
+
DECLARE_MSM_GPIO_PINS(152);
449
+
DECLARE_MSM_GPIO_PINS(153);
450
+
DECLARE_MSM_GPIO_PINS(154);
451
+
DECLARE_MSM_GPIO_PINS(155);
452
+
DECLARE_MSM_GPIO_PINS(156);
453
+
DECLARE_MSM_GPIO_PINS(157);
454
+
DECLARE_MSM_GPIO_PINS(158);
455
+
DECLARE_MSM_GPIO_PINS(159);
456
+
DECLARE_MSM_GPIO_PINS(160);
457
+
DECLARE_MSM_GPIO_PINS(161);
458
+
DECLARE_MSM_GPIO_PINS(162);
459
+
DECLARE_MSM_GPIO_PINS(163);
460
+
DECLARE_MSM_GPIO_PINS(164);
461
+
DECLARE_MSM_GPIO_PINS(165);
462
+
DECLARE_MSM_GPIO_PINS(166);
463
+
DECLARE_MSM_GPIO_PINS(167);
464
+
DECLARE_MSM_GPIO_PINS(168);
465
+
DECLARE_MSM_GPIO_PINS(169);
466
+
DECLARE_MSM_GPIO_PINS(170);
467
+
DECLARE_MSM_GPIO_PINS(171);
468
+
DECLARE_MSM_GPIO_PINS(172);
469
+
DECLARE_MSM_GPIO_PINS(173);
470
+
DECLARE_MSM_GPIO_PINS(174);
471
+
DECLARE_MSM_GPIO_PINS(175);
472
+
DECLARE_MSM_GPIO_PINS(176);
473
+
DECLARE_MSM_GPIO_PINS(177);
474
+
DECLARE_MSM_GPIO_PINS(178);
475
+
DECLARE_MSM_GPIO_PINS(179);
476
+
DECLARE_MSM_GPIO_PINS(180);
477
+
DECLARE_MSM_GPIO_PINS(181);
478
+
DECLARE_MSM_GPIO_PINS(182);
479
+
DECLARE_MSM_GPIO_PINS(183);
480
+
DECLARE_MSM_GPIO_PINS(184);
481
+
482
+
static const unsigned int ufs_reset_pins[] = { 185 };
483
+
484
+
enum eliza_functions {
485
+
msm_mux_gpio,
486
+
msm_mux_aoss_cti,
487
+
msm_mux_atest_char,
488
+
msm_mux_atest_usb,
489
+
msm_mux_audio_ext_mclk0,
490
+
msm_mux_audio_ref_clk,
491
+
msm_mux_cam_mclk,
492
+
msm_mux_cci_async_in,
493
+
msm_mux_cci_i2c_scl,
494
+
msm_mux_cci_i2c_sda,
495
+
msm_mux_cci_timer,
496
+
msm_mux_coex_uart1_rx,
497
+
msm_mux_coex_uart1_tx,
498
+
msm_mux_coex_uart2_rx,
499
+
msm_mux_coex_uart2_tx,
500
+
msm_mux_dbg_out_clk,
501
+
msm_mux_ddr_bist_complete,
502
+
msm_mux_ddr_bist_fail,
503
+
msm_mux_ddr_bist_start,
504
+
msm_mux_ddr_bist_stop,
505
+
msm_mux_ddr_pxi0,
506
+
msm_mux_ddr_pxi1,
507
+
msm_mux_dp0_hot,
508
+
msm_mux_egpio,
509
+
msm_mux_gcc_gp1,
510
+
msm_mux_gcc_gp2,
511
+
msm_mux_gcc_gp3,
512
+
msm_mux_gnss_adc0,
513
+
msm_mux_gnss_adc1,
514
+
msm_mux_hdmi_ddc_scl,
515
+
msm_mux_hdmi_ddc_sda,
516
+
msm_mux_hdmi_dtest0,
517
+
msm_mux_hdmi_dtest1,
518
+
msm_mux_hdmi_hot_plug,
519
+
msm_mux_hdmi_pixel_clk,
520
+
msm_mux_hdmi_rcv_det,
521
+
msm_mux_hdmi_tx_cec,
522
+
msm_mux_host2wlan_sol,
523
+
msm_mux_i2s0_data0,
524
+
msm_mux_i2s0_data1,
525
+
msm_mux_i2s0_sck,
526
+
msm_mux_i2s0_ws,
527
+
msm_mux_ibi_i3c,
528
+
msm_mux_jitter_bist,
529
+
msm_mux_mdp_esync0_out,
530
+
msm_mux_mdp_esync1_out,
531
+
msm_mux_mdp_vsync,
532
+
msm_mux_mdp_vsync0_out,
533
+
msm_mux_mdp_vsync11_out,
534
+
msm_mux_mdp_vsync1_out,
535
+
msm_mux_mdp_vsync2_out,
536
+
msm_mux_mdp_vsync3_out,
537
+
msm_mux_mdp_vsync_e,
538
+
msm_mux_nav_gpio0,
539
+
msm_mux_nav_gpio1,
540
+
msm_mux_nav_gpio2,
541
+
msm_mux_nav_gpio3,
542
+
msm_mux_pcie0_clk_req_n,
543
+
msm_mux_pcie1_clk_req_n,
544
+
msm_mux_phase_flag,
545
+
msm_mux_pll_bist_sync,
546
+
msm_mux_pll_clk_aux,
547
+
msm_mux_prng_rosc0,
548
+
msm_mux_prng_rosc1,
549
+
msm_mux_prng_rosc2,
550
+
msm_mux_prng_rosc3,
551
+
msm_mux_qdss_cti,
552
+
msm_mux_qdss_gpio_traceclk,
553
+
msm_mux_qdss_gpio_tracectl,
554
+
msm_mux_qdss_gpio_tracedata,
555
+
msm_mux_qlink_big_enable,
556
+
msm_mux_qlink_big_request,
557
+
msm_mux_qlink_little_enable,
558
+
msm_mux_qlink_little_request,
559
+
msm_mux_qlink_wmss,
560
+
msm_mux_qspi0,
561
+
msm_mux_qspi_clk,
562
+
msm_mux_qspi_cs,
563
+
msm_mux_qup1_se0,
564
+
msm_mux_qup1_se1,
565
+
msm_mux_qup1_se2,
566
+
msm_mux_qup1_se3,
567
+
msm_mux_qup1_se4,
568
+
msm_mux_qup1_se5,
569
+
msm_mux_qup1_se6,
570
+
msm_mux_qup1_se7,
571
+
msm_mux_qup2_se0,
572
+
msm_mux_qup2_se1,
573
+
msm_mux_qup2_se2,
574
+
msm_mux_qup2_se3,
575
+
msm_mux_qup2_se4,
576
+
msm_mux_qup2_se5,
577
+
msm_mux_qup2_se6,
578
+
msm_mux_qup2_se7,
579
+
msm_mux_resout_gpio,
580
+
msm_mux_sd_write_protect,
581
+
msm_mux_sdc1,
582
+
msm_mux_sdc2,
583
+
msm_mux_sdc2_fb_clk,
584
+
msm_mux_tb_trig_sdc1,
585
+
msm_mux_tb_trig_sdc2,
586
+
msm_mux_tmess_prng0,
587
+
msm_mux_tmess_prng1,
588
+
msm_mux_tmess_prng2,
589
+
msm_mux_tmess_prng3,
590
+
msm_mux_tsense_pwm1,
591
+
msm_mux_tsense_pwm2,
592
+
msm_mux_tsense_pwm3,
593
+
msm_mux_tsense_pwm4,
594
+
msm_mux_uim0_clk,
595
+
msm_mux_uim0_data,
596
+
msm_mux_uim0_present,
597
+
msm_mux_uim0_reset,
598
+
msm_mux_uim1_clk,
599
+
msm_mux_uim1_data,
600
+
msm_mux_uim1_present,
601
+
msm_mux_uim1_reset,
602
+
msm_mux_usb0_hs,
603
+
msm_mux_usb_phy,
604
+
msm_mux_vfr_0,
605
+
msm_mux_vfr_1,
606
+
msm_mux_vsense_trigger_mirnat,
607
+
msm_mux_wcn_sw_ctrl,
608
+
msm_mux__,
609
+
};
610
+
611
+
static const char *const gpio_groups[] = {
612
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
613
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
614
+
"gpio12", "gpio13", "gpio16", "gpio17", "gpio18", "gpio19",
615
+
"gpio20", "gpio21", "gpio22", "gpio23", "gpio26", "gpio27",
616
+
"gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
617
+
"gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
618
+
"gpio40", "gpio42", "gpio44", "gpio45", "gpio46", "gpio47",
619
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
620
+
"gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
621
+
"gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
622
+
"gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
623
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
624
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio84",
625
+
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90",
626
+
"gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
627
+
"gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102",
628
+
"gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108",
629
+
"gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114",
630
+
"gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
631
+
"gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126",
632
+
"gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132",
633
+
"gpio133", "gpio134", "gpio135", "gpio138", "gpio139", "gpio140",
634
+
"gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
635
+
"gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
636
+
"gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
637
+
"gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
638
+
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
639
+
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
640
+
"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
641
+
"gpio184",
642
+
};
643
+
644
+
static const char *const aoss_cti_groups[] = {
645
+
"gpio0", "gpio1", "gpio26", "gpio27",
646
+
};
647
+
648
+
static const char *const atest_char_groups[] = {
649
+
"gpio71", "gpio70", "gpio72", "gpio74", "gpio73",
650
+
};
651
+
652
+
static const char *const atest_usb_groups[] = {
653
+
"gpio55", "gpio54",
654
+
};
655
+
656
+
static const char *const audio_ext_mclk0_groups[] = {
657
+
"gpio69",
658
+
};
659
+
660
+
static const char *const audio_ref_clk_groups[] = {
661
+
"gpio32",
662
+
};
663
+
664
+
static const char *const cam_mclk_groups[] = {
665
+
"gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
666
+
};
667
+
668
+
static const char *const cci_async_in_groups[] = {
669
+
"gpio115", "gpio31", "gpio30",
670
+
};
671
+
672
+
static const char *const cci_i2c_scl_groups[] = {
673
+
"gpio71", "gpio73", "gpio75", "gpio77",
674
+
};
675
+
676
+
static const char *const cci_i2c_sda_groups[] = {
677
+
"gpio70", "gpio72", "gpio74", "gpio76",
678
+
};
679
+
680
+
static const char *const cci_timer_groups[] = {
681
+
"gpio76", "gpio63", "gpio125", "gpio126", "gpio127",
682
+
};
683
+
684
+
static const char *const coex_uart1_rx_groups[] = {
685
+
"gpio112",
686
+
};
687
+
688
+
static const char *const coex_uart1_tx_groups[] = {
689
+
"gpio111",
690
+
};
691
+
692
+
static const char *const coex_uart2_rx_groups[] = {
693
+
"gpio116",
694
+
};
695
+
696
+
static const char *const coex_uart2_tx_groups[] = {
697
+
"gpio100",
698
+
};
699
+
700
+
static const char *const dbg_out_clk_groups[] = {
701
+
"gpio81",
702
+
};
703
+
704
+
static const char *const ddr_bist_complete_groups[] = {
705
+
"gpio52",
706
+
};
707
+
708
+
static const char *const ddr_bist_fail_groups[] = {
709
+
"gpio147",
710
+
};
711
+
712
+
static const char *const ddr_bist_start_groups[] = {
713
+
"gpio34",
714
+
};
715
+
716
+
static const char *const ddr_bist_stop_groups[] = {
717
+
"gpio53",
718
+
};
719
+
720
+
static const char *const ddr_pxi0_groups[] = {
721
+
"gpio54", "gpio55",
722
+
};
723
+
724
+
static const char *const ddr_pxi1_groups[] = {
725
+
"gpio40", "gpio42",
726
+
};
727
+
728
+
static const char *const dp0_hot_groups[] = {
729
+
"gpio55",
730
+
};
731
+
732
+
static const char *const egpio_groups[] = {
733
+
"gpio28", "gpio29", "gpio30", "gpio31", "gpio138", "gpio139",
734
+
"gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145",
735
+
"gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151",
736
+
"gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157",
737
+
"gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163",
738
+
"gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169",
739
+
"gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175",
740
+
"gpio176", "gpio177", "gpio178", "gpio179", "gpio180", "gpio181",
741
+
"gpio182", "gpio184",
742
+
};
743
+
744
+
static const char *const gcc_gp1_groups[] = {
745
+
"gpio27", "gpio53",
746
+
};
747
+
748
+
static const char *const gcc_gp2_groups[] = {
749
+
"gpio32", "gpio35",
750
+
};
751
+
752
+
static const char *const gcc_gp3_groups[] = {
753
+
"gpio30", "gpio33",
754
+
};
755
+
756
+
static const char *const gnss_adc0_groups[] = {
757
+
"gpio42", "gpio55",
758
+
};
759
+
760
+
static const char *const gnss_adc1_groups[] = {
761
+
"gpio40", "gpio54",
762
+
};
763
+
764
+
static const char *const hdmi_ddc_scl_groups[] = {
765
+
"gpio6",
766
+
};
767
+
768
+
static const char *const hdmi_ddc_sda_groups[] = {
769
+
"gpio7",
770
+
};
771
+
772
+
static const char *const hdmi_dtest0_groups[] = {
773
+
"gpio132",
774
+
};
775
+
776
+
static const char *const hdmi_dtest1_groups[] = {
777
+
"gpio133",
778
+
};
779
+
780
+
static const char *const hdmi_hot_plug_groups[] = {
781
+
"gpio47",
782
+
};
783
+
784
+
static const char *const hdmi_pixel_clk_groups[] = {
785
+
"gpio18",
786
+
};
787
+
788
+
static const char *const hdmi_rcv_det_groups[] = {
789
+
"gpio19",
790
+
};
791
+
792
+
static const char *const hdmi_tx_cec_groups[] = {
793
+
"gpio46",
794
+
};
795
+
796
+
static const char *const host2wlan_sol_groups[] = {
797
+
"gpio33",
798
+
};
799
+
800
+
static const char *const i2s0_data0_groups[] = {
801
+
"gpio64",
802
+
};
803
+
804
+
static const char *const i2s0_data1_groups[] = {
805
+
"gpio63",
806
+
};
807
+
808
+
static const char *const i2s0_sck_groups[] = {
809
+
"gpio60",
810
+
};
811
+
812
+
static const char *const i2s0_ws_groups[] = {
813
+
"gpio61",
814
+
};
815
+
816
+
static const char *const ibi_i3c_groups[] = {
817
+
"gpio0", "gpio1", "gpio4", "gpio5", "gpio12", "gpio13",
818
+
"gpio28", "gpio29", "gpio32", "gpio33", "gpio36", "gpio37",
819
+
};
820
+
821
+
static const char *const jitter_bist_groups[] = {
822
+
"gpio77",
823
+
};
824
+
825
+
static const char *const mdp_esync0_out_groups[] = {
826
+
"gpio13",
827
+
};
828
+
829
+
static const char *const mdp_esync1_out_groups[] = {
830
+
"gpio12",
831
+
};
832
+
833
+
static const char *const mdp_vsync_groups[] = {
834
+
"gpio16", "gpio17", "gpio79", "gpio100", "gpio120", "gpio121",
835
+
};
836
+
837
+
static const char *const mdp_vsync0_out_groups[] = {
838
+
"gpio17",
839
+
};
840
+
841
+
static const char *const mdp_vsync11_out_groups[] = {
842
+
"gpio27",
843
+
};
844
+
845
+
static const char *const mdp_vsync1_out_groups[] = {
846
+
"gpio17",
847
+
};
848
+
849
+
static const char *const mdp_vsync2_out_groups[] = {
850
+
"gpio16",
851
+
};
852
+
853
+
static const char *const mdp_vsync3_out_groups[] = {
854
+
"gpio16",
855
+
};
856
+
857
+
static const char *const mdp_vsync_e_groups[] = {
858
+
"gpio13",
859
+
};
860
+
861
+
static const char *const nav_gpio0_groups[] = {
862
+
"gpio119",
863
+
};
864
+
865
+
static const char *const nav_gpio1_groups[] = {
866
+
"gpio117",
867
+
};
868
+
869
+
static const char *const nav_gpio2_groups[] = {
870
+
"gpio118",
871
+
};
872
+
873
+
static const char *const nav_gpio3_groups[] = {
874
+
"gpio113",
875
+
};
876
+
877
+
static const char *const pcie0_clk_req_n_groups[] = {
878
+
"gpio80",
879
+
};
880
+
881
+
static const char *const pcie1_clk_req_n_groups[] = {
882
+
"gpio52",
883
+
};
884
+
885
+
static const char *const phase_flag_groups[] = {
886
+
"gpio71", "gpio70", "gpio174", "gpio175", "gpio172", "gpio171",
887
+
"gpio170", "gpio169", "gpio168", "gpio167", "gpio166", "gpio165",
888
+
"gpio182", "gpio164", "gpio163", "gpio162", "gpio161", "gpio160",
889
+
"gpio159", "gpio158", "gpio157", "gpio80", "gpio78", "gpio181",
890
+
"gpio76", "gpio75", "gpio180", "gpio179", "gpio178", "gpio177",
891
+
"gpio176", "gpio173",
892
+
};
893
+
894
+
static const char *const pll_bist_sync_groups[] = {
895
+
"gpio184",
896
+
};
897
+
898
+
static const char *const pll_clk_aux_groups[] = {
899
+
"gpio135",
900
+
};
901
+
902
+
static const char *const prng_rosc0_groups[] = {
903
+
"gpio67",
904
+
};
905
+
906
+
static const char *const prng_rosc1_groups[] = {
907
+
"gpio69",
908
+
};
909
+
910
+
static const char *const prng_rosc2_groups[] = {
911
+
"gpio76",
912
+
};
913
+
914
+
static const char *const prng_rosc3_groups[] = {
915
+
"gpio74",
916
+
};
917
+
918
+
static const char *const qdss_cti_groups[] = {
919
+
"gpio18", "gpio19", "gpio32", "gpio73",
920
+
"gpio74", "gpio154", "gpio176", "gpio184",
921
+
};
922
+
923
+
static const char *const qdss_gpio_traceclk_groups[] = {
924
+
"gpio54", "gpio147",
925
+
};
926
+
927
+
static const char *const qdss_gpio_tracectl_groups[] = {
928
+
"gpio72", "gpio144",
929
+
};
930
+
931
+
static const char *const qdss_gpio_tracedata_groups[] = {
932
+
"gpio30", "gpio31", "gpio34", "gpio35", "gpio40", "gpio42",
933
+
"gpio52", "gpio53", "gpio65", "gpio66", "gpio67", "gpio114",
934
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio145", "gpio146",
935
+
"gpio155", "gpio156", "gpio163", "gpio164", "gpio167", "gpio168",
936
+
"gpio169", "gpio170", "gpio178", "gpio179", "gpio180", "gpio181",
937
+
"gpio182",
938
+
};
939
+
940
+
static const char *const qlink_big_enable_groups[] = {
941
+
"gpio96",
942
+
};
943
+
944
+
static const char *const qlink_big_request_groups[] = {
945
+
"gpio95",
946
+
};
947
+
948
+
static const char *const qlink_little_enable_groups[] = {
949
+
"gpio93",
950
+
};
951
+
952
+
static const char *const qlink_little_request_groups[] = {
953
+
"gpio92",
954
+
};
955
+
956
+
static const char *const qlink_wmss_groups[] = {
957
+
"gpio94",
958
+
};
959
+
960
+
static const char *const qspi0_groups[] = {
961
+
"gpio79", "gpio116", "gpio115", "gpio97", "gpio98",
962
+
};
963
+
964
+
static const char *const qspi_clk_groups[] = {
965
+
"gpio99",
966
+
};
967
+
968
+
static const char *const qspi_cs_groups[] = {
969
+
"gpio100",
970
+
};
971
+
972
+
static const char *const qup1_se0_groups[] = {
973
+
"gpio28", "gpio29", "gpio30", "gpio31",
974
+
};
975
+
976
+
static const char *const qup1_se1_groups[] = {
977
+
"gpio32", "gpio33", "gpio34", "gpio35",
978
+
};
979
+
980
+
static const char *const qup1_se2_groups[] = {
981
+
"gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30",
982
+
};
983
+
984
+
static const char *const qup1_se3_groups[] = {
985
+
"gpio44", "gpio45", "gpio46", "gpio47",
986
+
};
987
+
988
+
static const char *const qup1_se4_groups[] = {
989
+
"gpio36", "gpio37", "gpio37", "gpio36",
990
+
};
991
+
992
+
static const char *const qup1_se5_groups[] = {
993
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio34", "gpio35",
994
+
};
995
+
996
+
static const char *const qup1_se6_groups[] = {
997
+
"gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55",
998
+
};
999
+
1000
+
static const char *const qup1_se7_groups[] = {
1001
+
"gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78",
1002
+
};
1003
+
1004
+
static const char *const qup2_se0_groups[] = {
1005
+
"gpio0", "gpio1", "gpio2", "gpio3",
1006
+
};
1007
+
1008
+
static const char *const qup2_se1_groups[] = {
1009
+
"gpio4", "gpio5", "gpio6", "gpio7",
1010
+
};
1011
+
1012
+
static const char *const qup2_se2_groups[] = {
1013
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio16", "gpio17", "gpio18",
1014
+
};
1015
+
1016
+
static const char *const qup2_se3_groups[] = {
1017
+
"gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116",
1018
+
};
1019
+
1020
+
static const char *const qup2_se4_groups[] = {
1021
+
"gpio12", "gpio13", "gpio26", "gpio27",
1022
+
};
1023
+
1024
+
static const char *const qup2_se5_groups[] = {
1025
+
"gpio16", "gpio17", "gpio18", "gpio19",
1026
+
};
1027
+
1028
+
static const char *const qup2_se6_groups[] = {
1029
+
"gpio20", "gpio21", "gpio22", "gpio23",
1030
+
};
1031
+
1032
+
static const char *const qup2_se7_groups[] = {
1033
+
"gpio27", "gpio26", "gpio13", "gpio12",
1034
+
};
1035
+
1036
+
static const char *const resout_gpio_groups[] = {
1037
+
"gpio63",
1038
+
"gpio69",
1039
+
"gpio175",
1040
+
};
1041
+
1042
+
static const char *const sd_write_protect_groups[] = {
1043
+
"gpio57",
1044
+
};
1045
+
1046
+
static const char *const sdc1_groups[] = {
1047
+
"gpio121", "gpio123", "gpio124", "gpio125",
1048
+
"gpio126", "gpio127", "gpio128", "gpio129",
1049
+
"gpio130", "gpio131", "gpio120",
1050
+
};
1051
+
1052
+
static const char *const sdc2_groups[] = {
1053
+
"gpio38", "gpio39", "gpio48", "gpio49",
1054
+
"gpio51", "gpio62",
1055
+
};
1056
+
1057
+
static const char *const sdc2_fb_clk_groups[] = {
1058
+
"gpio50",
1059
+
};
1060
+
1061
+
static const char *const tb_trig_sdc1_groups[] = {
1062
+
"gpio34",
1063
+
};
1064
+
1065
+
static const char *const tb_trig_sdc2_groups[] = {
1066
+
"gpio35",
1067
+
};
1068
+
1069
+
static const char *const tmess_prng0_groups[] = {
1070
+
"gpio73",
1071
+
};
1072
+
1073
+
static const char *const tmess_prng1_groups[] = {
1074
+
"gpio72",
1075
+
};
1076
+
1077
+
static const char *const tmess_prng2_groups[] = {
1078
+
"gpio70",
1079
+
};
1080
+
1081
+
static const char *const tmess_prng3_groups[] = {
1082
+
"gpio71",
1083
+
};
1084
+
1085
+
static const char *const tsense_pwm1_groups[] = {
1086
+
"gpio56",
1087
+
};
1088
+
1089
+
static const char *const tsense_pwm2_groups[] = {
1090
+
"gpio56",
1091
+
};
1092
+
1093
+
static const char *const tsense_pwm3_groups[] = {
1094
+
"gpio56",
1095
+
};
1096
+
1097
+
static const char *const tsense_pwm4_groups[] = {
1098
+
"gpio56",
1099
+
};
1100
+
1101
+
static const char *const uim0_clk_groups[] = {
1102
+
"gpio85",
1103
+
};
1104
+
1105
+
static const char *const uim0_data_groups[] = {
1106
+
"gpio84",
1107
+
};
1108
+
1109
+
static const char *const uim0_present_groups[] = {
1110
+
"gpio87",
1111
+
};
1112
+
1113
+
static const char *const uim0_reset_groups[] = {
1114
+
"gpio86",
1115
+
};
1116
+
1117
+
static const char *const uim1_clk_groups[] = {
1118
+
"gpio98", "gpio89",
1119
+
};
1120
+
1121
+
static const char *const uim1_data_groups[] = {
1122
+
"gpio97", "gpio88",
1123
+
};
1124
+
1125
+
static const char *const uim1_present_groups[] = {
1126
+
"gpio100", "gpio91",
1127
+
};
1128
+
1129
+
static const char *const uim1_reset_groups[] = {
1130
+
"gpio99", "gpio90",
1131
+
};
1132
+
1133
+
static const char *const usb0_hs_groups[] = {
1134
+
"gpio56",
1135
+
};
1136
+
1137
+
static const char *const usb_phy_groups[] = {
1138
+
"gpio122",
1139
+
};
1140
+
1141
+
static const char *const vfr_0_groups[] = {
1142
+
"gpio63",
1143
+
};
1144
+
1145
+
static const char *const vfr_1_groups[] = {
1146
+
"gpio117",
1147
+
};
1148
+
1149
+
static const char *const vsense_trigger_mirnat_groups[] = {
1150
+
"gpio52",
1151
+
};
1152
+
1153
+
static const char *const wcn_sw_ctrl_groups[] = {
1154
+
"gpio81",
1155
+
};
1156
+
1157
+
static const struct pinfunction eliza_functions[] = {
1158
+
MSM_GPIO_PIN_FUNCTION(gpio),
1159
+
MSM_PIN_FUNCTION(aoss_cti),
1160
+
MSM_PIN_FUNCTION(atest_char),
1161
+
MSM_PIN_FUNCTION(atest_usb),
1162
+
MSM_PIN_FUNCTION(audio_ext_mclk0),
1163
+
MSM_PIN_FUNCTION(audio_ref_clk),
1164
+
MSM_PIN_FUNCTION(cam_mclk),
1165
+
MSM_PIN_FUNCTION(cci_async_in),
1166
+
MSM_PIN_FUNCTION(cci_i2c_scl),
1167
+
MSM_PIN_FUNCTION(cci_i2c_sda),
1168
+
MSM_PIN_FUNCTION(cci_timer),
1169
+
MSM_PIN_FUNCTION(coex_uart1_rx),
1170
+
MSM_PIN_FUNCTION(coex_uart1_tx),
1171
+
MSM_PIN_FUNCTION(coex_uart2_rx),
1172
+
MSM_PIN_FUNCTION(coex_uart2_tx),
1173
+
MSM_PIN_FUNCTION(dbg_out_clk),
1174
+
MSM_PIN_FUNCTION(ddr_bist_complete),
1175
+
MSM_PIN_FUNCTION(ddr_bist_fail),
1176
+
MSM_PIN_FUNCTION(ddr_bist_start),
1177
+
MSM_PIN_FUNCTION(ddr_bist_stop),
1178
+
MSM_PIN_FUNCTION(ddr_pxi0),
1179
+
MSM_PIN_FUNCTION(ddr_pxi1),
1180
+
MSM_PIN_FUNCTION(dp0_hot),
1181
+
MSM_PIN_FUNCTION(egpio),
1182
+
MSM_PIN_FUNCTION(gcc_gp1),
1183
+
MSM_PIN_FUNCTION(gcc_gp2),
1184
+
MSM_PIN_FUNCTION(gcc_gp3),
1185
+
MSM_PIN_FUNCTION(gnss_adc0),
1186
+
MSM_PIN_FUNCTION(gnss_adc1),
1187
+
MSM_PIN_FUNCTION(hdmi_ddc_scl),
1188
+
MSM_PIN_FUNCTION(hdmi_ddc_sda),
1189
+
MSM_PIN_FUNCTION(hdmi_dtest0),
1190
+
MSM_PIN_FUNCTION(hdmi_dtest1),
1191
+
MSM_PIN_FUNCTION(hdmi_hot_plug),
1192
+
MSM_PIN_FUNCTION(hdmi_pixel_clk),
1193
+
MSM_PIN_FUNCTION(hdmi_rcv_det),
1194
+
MSM_PIN_FUNCTION(hdmi_tx_cec),
1195
+
MSM_PIN_FUNCTION(host2wlan_sol),
1196
+
MSM_PIN_FUNCTION(i2s0_data0),
1197
+
MSM_PIN_FUNCTION(i2s0_data1),
1198
+
MSM_PIN_FUNCTION(i2s0_sck),
1199
+
MSM_PIN_FUNCTION(i2s0_ws),
1200
+
MSM_PIN_FUNCTION(ibi_i3c),
1201
+
MSM_PIN_FUNCTION(jitter_bist),
1202
+
MSM_PIN_FUNCTION(mdp_esync0_out),
1203
+
MSM_PIN_FUNCTION(mdp_esync1_out),
1204
+
MSM_PIN_FUNCTION(mdp_vsync),
1205
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
1206
+
MSM_PIN_FUNCTION(mdp_vsync11_out),
1207
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
1208
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
1209
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
1210
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1211
+
MSM_PIN_FUNCTION(nav_gpio0),
1212
+
MSM_PIN_FUNCTION(nav_gpio1),
1213
+
MSM_PIN_FUNCTION(nav_gpio2),
1214
+
MSM_PIN_FUNCTION(nav_gpio3),
1215
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
1216
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
1217
+
MSM_PIN_FUNCTION(phase_flag),
1218
+
MSM_PIN_FUNCTION(pll_bist_sync),
1219
+
MSM_PIN_FUNCTION(pll_clk_aux),
1220
+
MSM_PIN_FUNCTION(prng_rosc0),
1221
+
MSM_PIN_FUNCTION(prng_rosc1),
1222
+
MSM_PIN_FUNCTION(prng_rosc2),
1223
+
MSM_PIN_FUNCTION(prng_rosc3),
1224
+
MSM_PIN_FUNCTION(qdss_cti),
1225
+
MSM_PIN_FUNCTION(qdss_gpio_traceclk),
1226
+
MSM_PIN_FUNCTION(qdss_gpio_tracectl),
1227
+
MSM_PIN_FUNCTION(qdss_gpio_tracedata),
1228
+
MSM_PIN_FUNCTION(qlink_big_enable),
1229
+
MSM_PIN_FUNCTION(qlink_big_request),
1230
+
MSM_PIN_FUNCTION(qlink_little_enable),
1231
+
MSM_PIN_FUNCTION(qlink_little_request),
1232
+
MSM_PIN_FUNCTION(qlink_wmss),
1233
+
MSM_PIN_FUNCTION(qspi0),
1234
+
MSM_PIN_FUNCTION(qspi_clk),
1235
+
MSM_PIN_FUNCTION(qspi_cs),
1236
+
MSM_PIN_FUNCTION(qup1_se0),
1237
+
MSM_PIN_FUNCTION(qup1_se1),
1238
+
MSM_PIN_FUNCTION(qup1_se2),
1239
+
MSM_PIN_FUNCTION(qup1_se3),
1240
+
MSM_PIN_FUNCTION(qup1_se4),
1241
+
MSM_PIN_FUNCTION(qup1_se5),
1242
+
MSM_PIN_FUNCTION(qup1_se6),
1243
+
MSM_PIN_FUNCTION(qup1_se7),
1244
+
MSM_PIN_FUNCTION(qup2_se0),
1245
+
MSM_PIN_FUNCTION(qup2_se1),
1246
+
MSM_PIN_FUNCTION(qup2_se2),
1247
+
MSM_PIN_FUNCTION(qup2_se3),
1248
+
MSM_PIN_FUNCTION(qup2_se4),
1249
+
MSM_PIN_FUNCTION(qup2_se5),
1250
+
MSM_PIN_FUNCTION(qup2_se6),
1251
+
MSM_PIN_FUNCTION(qup2_se7),
1252
+
MSM_PIN_FUNCTION(resout_gpio),
1253
+
MSM_PIN_FUNCTION(sd_write_protect),
1254
+
MSM_PIN_FUNCTION(sdc1),
1255
+
MSM_PIN_FUNCTION(sdc2),
1256
+
MSM_PIN_FUNCTION(sdc2_fb_clk),
1257
+
MSM_PIN_FUNCTION(tb_trig_sdc1),
1258
+
MSM_PIN_FUNCTION(tb_trig_sdc2),
1259
+
MSM_PIN_FUNCTION(tmess_prng0),
1260
+
MSM_PIN_FUNCTION(tmess_prng1),
1261
+
MSM_PIN_FUNCTION(tmess_prng2),
1262
+
MSM_PIN_FUNCTION(tmess_prng3),
1263
+
MSM_PIN_FUNCTION(tsense_pwm1),
1264
+
MSM_PIN_FUNCTION(tsense_pwm2),
1265
+
MSM_PIN_FUNCTION(tsense_pwm3),
1266
+
MSM_PIN_FUNCTION(tsense_pwm4),
1267
+
MSM_PIN_FUNCTION(uim0_clk),
1268
+
MSM_PIN_FUNCTION(uim0_data),
1269
+
MSM_PIN_FUNCTION(uim0_present),
1270
+
MSM_PIN_FUNCTION(uim0_reset),
1271
+
MSM_PIN_FUNCTION(uim1_clk),
1272
+
MSM_PIN_FUNCTION(uim1_data),
1273
+
MSM_PIN_FUNCTION(uim1_present),
1274
+
MSM_PIN_FUNCTION(uim1_reset),
1275
+
MSM_PIN_FUNCTION(usb0_hs),
1276
+
MSM_PIN_FUNCTION(usb_phy),
1277
+
MSM_PIN_FUNCTION(vfr_0),
1278
+
MSM_PIN_FUNCTION(vfr_1),
1279
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1280
+
MSM_PIN_FUNCTION(wcn_sw_ctrl),
1281
+
};
1282
+
1283
+
/* Every pin is maintained as a single group, and missing or non-existing pin
1284
+
* would be maintained as dummy group to synchronize pin group index with
1285
+
* pin descriptor registered with pinctrl core.
1286
+
* Clients would not be able to request these dummy pin groups.
1287
+
*/
1288
+
static const struct msm_pingroup eliza_groups[] = {
1289
+
[0] = PINGROUP(0, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),
1290
+
[1] = PINGROUP(1, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _),
1291
+
[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, _),
1292
+
[3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, _),
1293
+
[4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1294
+
[5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1295
+
[6] = PINGROUP(6, qup2_se1, hdmi_ddc_scl, _, _, _, _, _, _, _, _, _),
1296
+
[7] = PINGROUP(7, qup2_se1, hdmi_ddc_sda, _, _, _, _, _, _, _, _, _),
1297
+
[8] = PINGROUP(8, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1298
+
[9] = PINGROUP(9, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1299
+
[10] = PINGROUP(10, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1300
+
[11] = PINGROUP(11, qup2_se2, _, _, _, _, _, _, _, _, _, _),
1301
+
[12] = PINGROUP(12, qup2_se4, ibi_i3c, mdp_esync1_out, qup2_se7, _, _, _, _, _, _, _),
1302
+
[13] = PINGROUP(13, qup2_se4, ibi_i3c, mdp_vsync_e, mdp_esync0_out, qup2_se7, _, _, _, _, _, _),
1303
+
[14] = PINGROUP(14, _, _, _, _, _, _, _, _, _, _, _),
1304
+
[15] = PINGROUP(15, _, _, _, _, _, _, _, _, _, _, _),
1305
+
[16] = PINGROUP(16, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, _, _, _, _, _, _),
1306
+
[17] = PINGROUP(17, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, _, _, _, _, _, _),
1307
+
[18] = PINGROUP(18, qup2_se5, qup2_se2, hdmi_pixel_clk, _, qdss_cti, _, _, _, _, _, _),
1308
+
[19] = PINGROUP(19, qup2_se5, hdmi_rcv_det, _, qdss_cti, _, _, _, _, _, _, _),
1309
+
[20] = PINGROUP(20, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1310
+
[21] = PINGROUP(21, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1311
+
[22] = PINGROUP(22, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1312
+
[23] = PINGROUP(23, qup2_se6, _, _, _, _, _, _, _, _, _, _),
1313
+
[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _, _, _),
1314
+
[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _, _, _),
1315
+
[26] = PINGROUP(26, qup2_se4, aoss_cti, qup2_se7, _, _, _, _, _, _, _, _),
1316
+
[27] = PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_gp1, _, _, _, _, _, _),
1317
+
[28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1318
+
[29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1319
+
[30] = PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, egpio),
1320
+
[31] = PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1321
+
[32] = PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti, _, _, _, _, _, _),
1322
+
[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
1323
+
[34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
1324
+
[35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
1325
+
[36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
1326
+
[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
1327
+
[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
1328
+
[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
1329
+
[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
1330
+
[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),
1331
+
[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
1332
+
[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),
1333
+
[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),
1334
+
[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),
1335
+
[46] = PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _),
1336
+
[47] = PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _),
1337
+
[48] = PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _),
1338
+
[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),
1339
+
[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),
1340
+
[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),
1341
+
[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
1342
+
[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
1343
+
[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
1344
+
[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
1345
+
[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),
1346
+
[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
1347
+
[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),
1348
+
[59] = PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _),
1349
+
[60] = PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _),
1350
+
[61] = PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _),
1351
+
[62] = PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _),
1352
+
[63] = PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _, _, _, _, _),
1353
+
[64] = PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _),
1354
+
[65] = PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),
1355
+
[66] = PINGROUP(66, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _),
1356
+
[67] = PINGROUP(67, cam_mclk, prng_rosc0, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
1357
+
[68] = PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1358
+
[69] = PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1, _, _, _, _, _, _, _),
1359
+
[70] = PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char, _, _, _, _, _, _),
1360
+
[71] = PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char, _, _, _, _, _, _),
1361
+
[72] = PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, atest_char, _, _, _, _, _, _, _),
1362
+
[73] = PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, _, _, _, _, _, _),
1363
+
[74] = PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _, _, _, _, _, _),
1364
+
[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),
1365
+
[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),
1366
+
[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),
1367
+
[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
1368
+
[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),
1369
+
[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
1370
+
[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),
1371
+
[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),
1372
+
[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),
1373
+
[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),
1374
+
[85] = PINGROUP(85, uim0_clk, _, _, _, _, _, _, _, _, _, _),
1375
+
[86] = PINGROUP(86, uim0_reset, _, _, _, _, _, _, _, _, _, _),
1376
+
[87] = PINGROUP(87, uim0_present, _, _, _, _, _, _, _, _, _, _),
1377
+
[88] = PINGROUP(88, uim1_data, _, _, _, _, _, _, _, _, _, _),
1378
+
[89] = PINGROUP(89, uim1_clk, _, _, _, _, _, _, _, _, _, _),
1379
+
[90] = PINGROUP(90, uim1_reset, _, _, _, _, _, _, _, _, _, _),
1380
+
[91] = PINGROUP(91, uim1_present, _, _, _, _, _, _, _, _, _, _),
1381
+
[92] = PINGROUP(92, qlink_little_request, _, _, _, _, _, _, _, _, _, _),
1382
+
[93] = PINGROUP(93, qlink_little_enable, _, _, _, _, _, _, _, _, _, _),
1383
+
[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),
1384
+
[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),
1385
+
[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),
1386
+
[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),
1387
+
[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),
1388
+
[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),
1389
+
[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),
1390
+
[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
1391
+
[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),
1392
+
[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),
1393
+
[104] = PINGROUP(104, _, _, _, _, _, _, _, _, _, _, _),
1394
+
[105] = PINGROUP(105, _, _, _, _, _, _, _, _, _, _, _),
1395
+
[106] = PINGROUP(106, _, _, _, _, _, _, _, _, _, _, _),
1396
+
[107] = PINGROUP(107, _, _, _, _, _, _, _, _, _, _, _),
1397
+
[108] = PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _),
1398
+
[109] = PINGROUP(109, _, _, _, _, _, _, _, _, _, _, _),
1399
+
[110] = PINGROUP(110, _, _, _, _, _, _, _, _, _, _, _),
1400
+
[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),
1401
+
[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),
1402
+
[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),
1403
+
[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
1404
+
[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),
1405
+
[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),
1406
+
[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),
1407
+
[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),
1408
+
[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),
1409
+
[120] = PINGROUP(120, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _),
1410
+
[121] = PINGROUP(121, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _),
1411
+
[122] = PINGROUP(122, usb_phy, _, _, _, _, _, _, _, _, _, _),
1412
+
[123] = PINGROUP(123, sdc1, _, _, _, _, _, _, _, _, _, _),
1413
+
[124] = PINGROUP(124, sdc1, _, _, _, _, _, _, _, _, _, _),
1414
+
[125] = PINGROUP(125, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),
1415
+
[126] = PINGROUP(126, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),
1416
+
[127] = PINGROUP(127, sdc1, cci_timer, _, _, _, _, _, _, _, _, _),
1417
+
[128] = PINGROUP(128, sdc1, _, _, _, _, _, _, _, _, _, _),
1418
+
[129] = PINGROUP(129, sdc1, _, _, _, _, _, _, _, _, _, _),
1419
+
[130] = PINGROUP(130, sdc1, _, _, _, _, _, _, _, _, _, _),
1420
+
[131] = PINGROUP(131, sdc1, _, _, _, _, _, _, _, _, _, _),
1421
+
[132] = PINGROUP(132, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest0, _, _, _, _, _, _, _),
1422
+
[133] = PINGROUP(133, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest1, _, _, _, _, _, _, _),
1423
+
[134] = PINGROUP(134, qup1_se5, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _),
1424
+
[135] = PINGROUP(135, qup1_se5, _, pll_clk_aux, qdss_gpio_tracedata, _, _, _, _, _, _, _),
1425
+
[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),
1426
+
[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),
1427
+
[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _, _, egpio),
1428
+
[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _, _, egpio),
1429
+
[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, egpio),
1430
+
[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio),
1431
+
[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio),
1432
+
[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio),
1433
+
[144] = PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
1434
+
[145] = PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, egpio),
1435
+
[146] = PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
1436
+
[147] = PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1437
+
[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio),
1438
+
[149] = PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio),
1439
+
[150] = PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio),
1440
+
[151] = PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio),
1441
+
[152] = PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio),
1442
+
[153] = PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio),
1443
+
[154] = PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _, _, egpio),
1444
+
[155] = PINGROUP(155, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
1445
+
[156] = PINGROUP(156, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, egpio),
1446
+
[157] = PINGROUP(157, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1447
+
[158] = PINGROUP(158, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1448
+
[159] = PINGROUP(159, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1449
+
[160] = PINGROUP(160, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1450
+
[161] = PINGROUP(161, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1451
+
[162] = PINGROUP(162, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1452
+
[163] = PINGROUP(163, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1453
+
[164] = PINGROUP(164, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1454
+
[165] = PINGROUP(165, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1455
+
[166] = PINGROUP(166, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1456
+
[167] = PINGROUP(167, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1457
+
[168] = PINGROUP(168, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1458
+
[169] = PINGROUP(169, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1459
+
[170] = PINGROUP(170, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1460
+
[171] = PINGROUP(171, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1461
+
[172] = PINGROUP(172, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1462
+
[173] = PINGROUP(173, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1463
+
[174] = PINGROUP(174, _, phase_flag, _, _, _, _, _, _, _, _, egpio),
1464
+
[175] = PINGROUP(175, resout_gpio, _, phase_flag, _, _, _, _, _, _, _, egpio),
1465
+
[176] = PINGROUP(176, _, phase_flag, qdss_cti, _, _, _, _, _, _, _, egpio),
1466
+
[177] = PINGROUP(177, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1467
+
[178] = PINGROUP(178, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1468
+
[179] = PINGROUP(179, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1469
+
[180] = PINGROUP(180, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1470
+
[181] = PINGROUP(181, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1471
+
[182] = PINGROUP(182, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),
1472
+
[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, _),
1473
+
[184] = PINGROUP(184, pll_bist_sync, qdss_cti, _, _, _, _, _, _, _, _, egpio),
1474
+
[185] = UFS_RESET(ufs_reset, 0xc9004, 0xca000),
1475
+
};
1476
+
1477
+
static const struct msm_gpio_wakeirq_map eliza_pdc_map[] = {
1478
+
{ 0, 82 }, { 3, 87 }, { 4, 90 }, { 6, 68 }, { 7, 153 },
1479
+
{ 11, 85 }, { 12, 107 }, { 13, 106 }, { 16, 88 }, { 17, 70 },
1480
+
{ 18, 134 }, { 19, 79 }, { 23, 80 }, { 26, 91 }, { 27, 74 },
1481
+
{ 28, 137 }, { 29, 138 }, { 30, 139 }, { 31, 140 }, { 32, 117 },
1482
+
{ 34, 100 }, { 35, 98 }, { 36, 141 }, { 39, 89 }, { 40, 142 },
1483
+
{ 42, 143 }, { 44, 101 }, { 45, 144 }, { 46, 145 }, { 47, 146 },
1484
+
{ 49, 75 }, { 51, 147 }, { 52, 148 }, { 53, 149 }, { 54, 150 },
1485
+
{ 55, 151 }, { 56, 152 }, { 58, 71 }, { 59, 155 }, { 63, 99 },
1486
+
{ 78, 156 }, { 79, 76 }, { 80, 157 }, { 81, 69 }, { 87, 158 },
1487
+
{ 91, 67 }, { 92, 159 }, { 95, 160 }, { 98, 161 }, { 99, 162 },
1488
+
{ 100, 83 }, { 108, 154 }, { 109, 84 }, { 112, 86 }, { 113, 92 },
1489
+
{ 114, 93 }, { 115, 110 }, { 116, 94 }, { 117, 77 }, { 118, 108 },
1490
+
{ 119, 95 }, { 120, 81 }, { 121, 96 }, { 122, 97 }, { 123, 102 },
1491
+
{ 125, 103 }, { 127, 104 }, { 128, 105 }, { 129, 78 }, { 130, 112 },
1492
+
{ 131, 113 }, { 133, 114 }, { 135, 115 }, { 139, 116 }, { 142, 118 },
1493
+
{ 145, 109 }, { 147, 72 }, { 149, 111 }, { 154, 122 }, { 157, 119 },
1494
+
{ 159, 120 }, { 161, 121 }, { 164, 123 }, { 165, 124 }, { 167, 125 },
1495
+
{ 170, 126 }, { 171, 73 }, { 172, 127 }, { 173, 128 }, { 174, 129 },
1496
+
{ 175, 130 }, { 176, 131 }, { 177, 132 }, { 179, 133 }, { 182, 135 },
1497
+
{ 184, 136 },
1498
+
};
1499
+
1500
+
static const struct msm_pinctrl_soc_data eliza_tlmm = {
1501
+
.pins = eliza_pins,
1502
+
.npins = ARRAY_SIZE(eliza_pins),
1503
+
.functions = eliza_functions,
1504
+
.nfunctions = ARRAY_SIZE(eliza_functions),
1505
+
.groups = eliza_groups,
1506
+
.ngroups = ARRAY_SIZE(eliza_groups),
1507
+
.ngpios = 186,
1508
+
.wakeirq_map = eliza_pdc_map,
1509
+
.nwakeirq_map = ARRAY_SIZE(eliza_pdc_map),
1510
+
.egpio_func = 11,
1511
+
};
1512
+
1513
+
static int eliza_tlmm_probe(struct platform_device *pdev)
1514
+
{
1515
+
return msm_pinctrl_probe(pdev, &eliza_tlmm);
1516
+
}
1517
+
1518
+
static const struct of_device_id eliza_tlmm_of_match[] = {
1519
+
{ .compatible = "qcom,eliza-tlmm", },
1520
+
{},
1521
+
};
1522
+
1523
+
static struct platform_driver eliza_tlmm_driver = {
1524
+
.driver = {
1525
+
.name = "eliza-tlmm",
1526
+
.of_match_table = eliza_tlmm_of_match,
1527
+
},
1528
+
.probe = eliza_tlmm_probe,
1529
+
};
1530
+
1531
+
static int __init eliza_tlmm_init(void)
1532
+
{
1533
+
return platform_driver_register(&eliza_tlmm_driver);
1534
+
}
1535
+
arch_initcall(eliza_tlmm_init);
1536
+
1537
+
static void __exit eliza_tlmm_exit(void)
1538
+
{
1539
+
platform_driver_unregister(&eliza_tlmm_driver);
1540
+
}
1541
+
module_exit(eliza_tlmm_exit);
1542
+
1543
+
MODULE_DESCRIPTION("QTI Eliza TLMM driver");
1544
+
MODULE_LICENSE("GPL");
1545
+
MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match);
+1
-4
drivers/pinctrl/qcom/pinctrl-glymur.c
+1
-4
drivers/pinctrl/qcom/pinctrl-glymur.c
···
21
21
.io_reg = 0x4 + REG_SIZE * id, \
22
22
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
23
23
.intr_status_reg = 0xc + REG_SIZE * id, \
24
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
25
24
.mux_bit = 2, \
26
25
.pull_bit = 0, \
27
26
.drv_bit = 6, \
···
63
64
.io_reg = 0, \
64
65
.intr_cfg_reg = 0, \
65
66
.intr_status_reg = 0, \
66
-
.intr_target_reg = 0, \
67
67
.mux_bit = -1, \
68
68
.pull_bit = pull, \
69
69
.drv_bit = drv, \
···
87
89
.io_reg = io, \
88
90
.intr_cfg_reg = 0, \
89
91
.intr_status_reg = 0, \
90
-
.intr_target_reg = 0, \
91
92
.mux_bit = -1, \
92
93
.pull_bit = 3, \
93
94
.drv_bit = 0, \
···
1809
1812
}
1810
1813
module_exit(glymur_tlmm_exit);
1811
1814
1812
-
MODULE_DESCRIPTION("QTI GLYMUR TLMM driver");
1815
+
MODULE_DESCRIPTION("QTI Glymur TLMM driver");
1813
1816
MODULE_LICENSE("GPL");
1814
1817
MODULE_DEVICE_TABLE(of, glymur_tlmm_of_match);
+1610
drivers/pinctrl/qcom/pinctrl-hawi.c
+1610
drivers/pinctrl/qcom/pinctrl-hawi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
14
+
{ \
15
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
16
+
gpio##id##_pins, \
17
+
ARRAY_SIZE(gpio##id##_pins)), \
18
+
.funcs = (int[]){ \
19
+
msm_mux_gpio, /* gpio mode */ \
20
+
msm_mux_##f1, \
21
+
msm_mux_##f2, \
22
+
msm_mux_##f3, \
23
+
msm_mux_##f4, \
24
+
msm_mux_##f5, \
25
+
msm_mux_##f6, \
26
+
msm_mux_##f7, \
27
+
msm_mux_##f8, \
28
+
msm_mux_##f9, \
29
+
msm_mux_##f10, \
30
+
msm_mux_##f11 /* egpio mode */ \
31
+
}, \
32
+
.nfuncs = 12, \
33
+
.ctl_reg = REG_SIZE * id, \
34
+
.io_reg = 0x4 + REG_SIZE * id, \
35
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
+
.intr_status_reg = 0xc + REG_SIZE * id, \
37
+
.mux_bit = 2, \
38
+
.pull_bit = 0, \
39
+
.drv_bit = 6, \
40
+
.egpio_enable = 12, \
41
+
.egpio_present = 11, \
42
+
.oe_bit = 9, \
43
+
.in_bit = 0, \
44
+
.out_bit = 1, \
45
+
.intr_enable_bit = 0, \
46
+
.intr_status_bit = 0, \
47
+
.intr_wakeup_present_bit = 6, \
48
+
.intr_wakeup_enable_bit = 7, \
49
+
.intr_target_bit = 8, \
50
+
.intr_target_kpss_val = 3, \
51
+
.intr_raw_status_bit = 4, \
52
+
.intr_polarity_bit = 1, \
53
+
.intr_detection_bit = 2, \
54
+
.intr_detection_width = 2, \
55
+
}
56
+
57
+
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
58
+
{ \
59
+
.grp = PINCTRL_PINGROUP(#pg_name, \
60
+
pg_name##_pins, \
61
+
ARRAY_SIZE(pg_name##_pins)), \
62
+
.ctl_reg = ctl, \
63
+
.io_reg = 0, \
64
+
.intr_cfg_reg = 0, \
65
+
.intr_status_reg = 0, \
66
+
.intr_target_reg = 0, \
67
+
.mux_bit = -1, \
68
+
.pull_bit = pull, \
69
+
.drv_bit = drv, \
70
+
.oe_bit = -1, \
71
+
.in_bit = -1, \
72
+
.out_bit = -1, \
73
+
.intr_enable_bit = -1, \
74
+
.intr_status_bit = -1, \
75
+
.intr_target_bit = -1, \
76
+
.intr_raw_status_bit = -1, \
77
+
.intr_polarity_bit = -1, \
78
+
.intr_detection_bit = -1, \
79
+
.intr_detection_width = -1, \
80
+
}
81
+
82
+
#define UFS_RESET(pg_name, ctl, io) \
83
+
{ \
84
+
.grp = PINCTRL_PINGROUP(#pg_name, \
85
+
pg_name##_pins, \
86
+
ARRAY_SIZE(pg_name##_pins)), \
87
+
.ctl_reg = ctl, \
88
+
.io_reg = io, \
89
+
.intr_cfg_reg = 0, \
90
+
.intr_status_reg = 0, \
91
+
.intr_target_reg = 0, \
92
+
.mux_bit = -1, \
93
+
.pull_bit = 3, \
94
+
.drv_bit = 0, \
95
+
.oe_bit = -1, \
96
+
.in_bit = -1, \
97
+
.out_bit = 0, \
98
+
.intr_enable_bit = -1, \
99
+
.intr_status_bit = -1, \
100
+
.intr_target_bit = -1, \
101
+
.intr_raw_status_bit = -1, \
102
+
.intr_polarity_bit = -1, \
103
+
.intr_detection_bit = -1, \
104
+
.intr_detection_width = -1, \
105
+
}
106
+
107
+
static const struct pinctrl_pin_desc hawi_pins[] = {
108
+
PINCTRL_PIN(0, "GPIO_0"),
109
+
PINCTRL_PIN(1, "GPIO_1"),
110
+
PINCTRL_PIN(2, "GPIO_2"),
111
+
PINCTRL_PIN(3, "GPIO_3"),
112
+
PINCTRL_PIN(4, "GPIO_4"),
113
+
PINCTRL_PIN(5, "GPIO_5"),
114
+
PINCTRL_PIN(6, "GPIO_6"),
115
+
PINCTRL_PIN(7, "GPIO_7"),
116
+
PINCTRL_PIN(8, "GPIO_8"),
117
+
PINCTRL_PIN(9, "GPIO_9"),
118
+
PINCTRL_PIN(10, "GPIO_10"),
119
+
PINCTRL_PIN(11, "GPIO_11"),
120
+
PINCTRL_PIN(12, "GPIO_12"),
121
+
PINCTRL_PIN(13, "GPIO_13"),
122
+
PINCTRL_PIN(14, "GPIO_14"),
123
+
PINCTRL_PIN(15, "GPIO_15"),
124
+
PINCTRL_PIN(16, "GPIO_16"),
125
+
PINCTRL_PIN(17, "GPIO_17"),
126
+
PINCTRL_PIN(18, "GPIO_18"),
127
+
PINCTRL_PIN(19, "GPIO_19"),
128
+
PINCTRL_PIN(20, "GPIO_20"),
129
+
PINCTRL_PIN(21, "GPIO_21"),
130
+
PINCTRL_PIN(22, "GPIO_22"),
131
+
PINCTRL_PIN(23, "GPIO_23"),
132
+
PINCTRL_PIN(24, "GPIO_24"),
133
+
PINCTRL_PIN(25, "GPIO_25"),
134
+
PINCTRL_PIN(26, "GPIO_26"),
135
+
PINCTRL_PIN(27, "GPIO_27"),
136
+
PINCTRL_PIN(28, "GPIO_28"),
137
+
PINCTRL_PIN(29, "GPIO_29"),
138
+
PINCTRL_PIN(30, "GPIO_30"),
139
+
PINCTRL_PIN(31, "GPIO_31"),
140
+
PINCTRL_PIN(32, "GPIO_32"),
141
+
PINCTRL_PIN(33, "GPIO_33"),
142
+
PINCTRL_PIN(34, "GPIO_34"),
143
+
PINCTRL_PIN(35, "GPIO_35"),
144
+
PINCTRL_PIN(36, "GPIO_36"),
145
+
PINCTRL_PIN(37, "GPIO_37"),
146
+
PINCTRL_PIN(38, "GPIO_38"),
147
+
PINCTRL_PIN(39, "GPIO_39"),
148
+
PINCTRL_PIN(40, "GPIO_40"),
149
+
PINCTRL_PIN(41, "GPIO_41"),
150
+
PINCTRL_PIN(42, "GPIO_42"),
151
+
PINCTRL_PIN(43, "GPIO_43"),
152
+
PINCTRL_PIN(44, "GPIO_44"),
153
+
PINCTRL_PIN(45, "GPIO_45"),
154
+
PINCTRL_PIN(46, "GPIO_46"),
155
+
PINCTRL_PIN(47, "GPIO_47"),
156
+
PINCTRL_PIN(48, "GPIO_48"),
157
+
PINCTRL_PIN(49, "GPIO_49"),
158
+
PINCTRL_PIN(50, "GPIO_50"),
159
+
PINCTRL_PIN(51, "GPIO_51"),
160
+
PINCTRL_PIN(52, "GPIO_52"),
161
+
PINCTRL_PIN(53, "GPIO_53"),
162
+
PINCTRL_PIN(54, "GPIO_54"),
163
+
PINCTRL_PIN(55, "GPIO_55"),
164
+
PINCTRL_PIN(56, "GPIO_56"),
165
+
PINCTRL_PIN(57, "GPIO_57"),
166
+
PINCTRL_PIN(58, "GPIO_58"),
167
+
PINCTRL_PIN(59, "GPIO_59"),
168
+
PINCTRL_PIN(60, "GPIO_60"),
169
+
PINCTRL_PIN(61, "GPIO_61"),
170
+
PINCTRL_PIN(62, "GPIO_62"),
171
+
PINCTRL_PIN(63, "GPIO_63"),
172
+
PINCTRL_PIN(64, "GPIO_64"),
173
+
PINCTRL_PIN(65, "GPIO_65"),
174
+
PINCTRL_PIN(66, "GPIO_66"),
175
+
PINCTRL_PIN(67, "GPIO_67"),
176
+
PINCTRL_PIN(68, "GPIO_68"),
177
+
PINCTRL_PIN(69, "GPIO_69"),
178
+
PINCTRL_PIN(70, "GPIO_70"),
179
+
PINCTRL_PIN(71, "GPIO_71"),
180
+
PINCTRL_PIN(72, "GPIO_72"),
181
+
PINCTRL_PIN(73, "GPIO_73"),
182
+
PINCTRL_PIN(74, "GPIO_74"),
183
+
PINCTRL_PIN(75, "GPIO_75"),
184
+
PINCTRL_PIN(76, "GPIO_76"),
185
+
PINCTRL_PIN(77, "GPIO_77"),
186
+
PINCTRL_PIN(78, "GPIO_78"),
187
+
PINCTRL_PIN(79, "GPIO_79"),
188
+
PINCTRL_PIN(80, "GPIO_80"),
189
+
PINCTRL_PIN(81, "GPIO_81"),
190
+
PINCTRL_PIN(82, "GPIO_82"),
191
+
PINCTRL_PIN(83, "GPIO_83"),
192
+
PINCTRL_PIN(84, "GPIO_84"),
193
+
PINCTRL_PIN(85, "GPIO_85"),
194
+
PINCTRL_PIN(86, "GPIO_86"),
195
+
PINCTRL_PIN(87, "GPIO_87"),
196
+
PINCTRL_PIN(88, "GPIO_88"),
197
+
PINCTRL_PIN(89, "GPIO_89"),
198
+
PINCTRL_PIN(90, "GPIO_90"),
199
+
PINCTRL_PIN(91, "GPIO_91"),
200
+
PINCTRL_PIN(92, "GPIO_92"),
201
+
PINCTRL_PIN(93, "GPIO_93"),
202
+
PINCTRL_PIN(94, "GPIO_94"),
203
+
PINCTRL_PIN(95, "GPIO_95"),
204
+
PINCTRL_PIN(96, "GPIO_96"),
205
+
PINCTRL_PIN(97, "GPIO_97"),
206
+
PINCTRL_PIN(98, "GPIO_98"),
207
+
PINCTRL_PIN(99, "GPIO_99"),
208
+
PINCTRL_PIN(100, "GPIO_100"),
209
+
PINCTRL_PIN(101, "GPIO_101"),
210
+
PINCTRL_PIN(102, "GPIO_102"),
211
+
PINCTRL_PIN(103, "GPIO_103"),
212
+
PINCTRL_PIN(104, "GPIO_104"),
213
+
PINCTRL_PIN(105, "GPIO_105"),
214
+
PINCTRL_PIN(106, "GPIO_106"),
215
+
PINCTRL_PIN(107, "GPIO_107"),
216
+
PINCTRL_PIN(108, "GPIO_108"),
217
+
PINCTRL_PIN(109, "GPIO_109"),
218
+
PINCTRL_PIN(110, "GPIO_110"),
219
+
PINCTRL_PIN(111, "GPIO_111"),
220
+
PINCTRL_PIN(112, "GPIO_112"),
221
+
PINCTRL_PIN(113, "GPIO_113"),
222
+
PINCTRL_PIN(114, "GPIO_114"),
223
+
PINCTRL_PIN(115, "GPIO_115"),
224
+
PINCTRL_PIN(116, "GPIO_116"),
225
+
PINCTRL_PIN(117, "GPIO_117"),
226
+
PINCTRL_PIN(118, "GPIO_118"),
227
+
PINCTRL_PIN(119, "GPIO_119"),
228
+
PINCTRL_PIN(120, "GPIO_120"),
229
+
PINCTRL_PIN(121, "GPIO_121"),
230
+
PINCTRL_PIN(122, "GPIO_122"),
231
+
PINCTRL_PIN(123, "GPIO_123"),
232
+
PINCTRL_PIN(124, "GPIO_124"),
233
+
PINCTRL_PIN(125, "GPIO_125"),
234
+
PINCTRL_PIN(126, "GPIO_126"),
235
+
PINCTRL_PIN(127, "GPIO_127"),
236
+
PINCTRL_PIN(128, "GPIO_128"),
237
+
PINCTRL_PIN(129, "GPIO_129"),
238
+
PINCTRL_PIN(130, "GPIO_130"),
239
+
PINCTRL_PIN(131, "GPIO_131"),
240
+
PINCTRL_PIN(132, "GPIO_132"),
241
+
PINCTRL_PIN(133, "GPIO_133"),
242
+
PINCTRL_PIN(134, "GPIO_134"),
243
+
PINCTRL_PIN(135, "GPIO_135"),
244
+
PINCTRL_PIN(136, "GPIO_136"),
245
+
PINCTRL_PIN(137, "GPIO_137"),
246
+
PINCTRL_PIN(138, "GPIO_138"),
247
+
PINCTRL_PIN(139, "GPIO_139"),
248
+
PINCTRL_PIN(140, "GPIO_140"),
249
+
PINCTRL_PIN(141, "GPIO_141"),
250
+
PINCTRL_PIN(142, "GPIO_142"),
251
+
PINCTRL_PIN(143, "GPIO_143"),
252
+
PINCTRL_PIN(144, "GPIO_144"),
253
+
PINCTRL_PIN(145, "GPIO_145"),
254
+
PINCTRL_PIN(146, "GPIO_146"),
255
+
PINCTRL_PIN(147, "GPIO_147"),
256
+
PINCTRL_PIN(148, "GPIO_148"),
257
+
PINCTRL_PIN(149, "GPIO_149"),
258
+
PINCTRL_PIN(150, "GPIO_150"),
259
+
PINCTRL_PIN(151, "GPIO_151"),
260
+
PINCTRL_PIN(152, "GPIO_152"),
261
+
PINCTRL_PIN(153, "GPIO_153"),
262
+
PINCTRL_PIN(154, "GPIO_154"),
263
+
PINCTRL_PIN(155, "GPIO_155"),
264
+
PINCTRL_PIN(156, "GPIO_156"),
265
+
PINCTRL_PIN(157, "GPIO_157"),
266
+
PINCTRL_PIN(158, "GPIO_158"),
267
+
PINCTRL_PIN(159, "GPIO_159"),
268
+
PINCTRL_PIN(160, "GPIO_160"),
269
+
PINCTRL_PIN(161, "GPIO_161"),
270
+
PINCTRL_PIN(162, "GPIO_162"),
271
+
PINCTRL_PIN(163, "GPIO_163"),
272
+
PINCTRL_PIN(164, "GPIO_164"),
273
+
PINCTRL_PIN(165, "GPIO_165"),
274
+
PINCTRL_PIN(166, "GPIO_166"),
275
+
PINCTRL_PIN(167, "GPIO_167"),
276
+
PINCTRL_PIN(168, "GPIO_168"),
277
+
PINCTRL_PIN(169, "GPIO_169"),
278
+
PINCTRL_PIN(170, "GPIO_170"),
279
+
PINCTRL_PIN(171, "GPIO_171"),
280
+
PINCTRL_PIN(172, "GPIO_172"),
281
+
PINCTRL_PIN(173, "GPIO_173"),
282
+
PINCTRL_PIN(174, "GPIO_174"),
283
+
PINCTRL_PIN(175, "GPIO_175"),
284
+
PINCTRL_PIN(176, "GPIO_176"),
285
+
PINCTRL_PIN(177, "GPIO_177"),
286
+
PINCTRL_PIN(178, "GPIO_178"),
287
+
PINCTRL_PIN(179, "GPIO_179"),
288
+
PINCTRL_PIN(180, "GPIO_180"),
289
+
PINCTRL_PIN(181, "GPIO_181"),
290
+
PINCTRL_PIN(182, "GPIO_182"),
291
+
PINCTRL_PIN(183, "GPIO_183"),
292
+
PINCTRL_PIN(184, "GPIO_184"),
293
+
PINCTRL_PIN(185, "GPIO_185"),
294
+
PINCTRL_PIN(186, "GPIO_186"),
295
+
PINCTRL_PIN(187, "GPIO_187"),
296
+
PINCTRL_PIN(188, "GPIO_188"),
297
+
PINCTRL_PIN(189, "GPIO_189"),
298
+
PINCTRL_PIN(190, "GPIO_190"),
299
+
PINCTRL_PIN(191, "GPIO_191"),
300
+
PINCTRL_PIN(192, "GPIO_192"),
301
+
PINCTRL_PIN(193, "GPIO_193"),
302
+
PINCTRL_PIN(194, "GPIO_194"),
303
+
PINCTRL_PIN(195, "GPIO_195"),
304
+
PINCTRL_PIN(196, "GPIO_196"),
305
+
PINCTRL_PIN(197, "GPIO_197"),
306
+
PINCTRL_PIN(198, "GPIO_198"),
307
+
PINCTRL_PIN(199, "GPIO_199"),
308
+
PINCTRL_PIN(200, "GPIO_200"),
309
+
PINCTRL_PIN(201, "GPIO_201"),
310
+
PINCTRL_PIN(202, "GPIO_202"),
311
+
PINCTRL_PIN(203, "GPIO_203"),
312
+
PINCTRL_PIN(204, "GPIO_204"),
313
+
PINCTRL_PIN(205, "GPIO_205"),
314
+
PINCTRL_PIN(206, "GPIO_206"),
315
+
PINCTRL_PIN(207, "GPIO_207"),
316
+
PINCTRL_PIN(208, "GPIO_208"),
317
+
PINCTRL_PIN(209, "GPIO_209"),
318
+
PINCTRL_PIN(210, "GPIO_210"),
319
+
PINCTRL_PIN(211, "GPIO_211"),
320
+
PINCTRL_PIN(212, "GPIO_212"),
321
+
PINCTRL_PIN(213, "GPIO_213"),
322
+
PINCTRL_PIN(214, "GPIO_214"),
323
+
PINCTRL_PIN(215, "GPIO_215"),
324
+
PINCTRL_PIN(216, "GPIO_216"),
325
+
PINCTRL_PIN(217, "GPIO_217"),
326
+
PINCTRL_PIN(218, "GPIO_218"),
327
+
PINCTRL_PIN(219, "GPIO_219"),
328
+
PINCTRL_PIN(220, "GPIO_220"),
329
+
PINCTRL_PIN(221, "GPIO_221"),
330
+
PINCTRL_PIN(222, "GPIO_222"),
331
+
PINCTRL_PIN(223, "GPIO_223"),
332
+
PINCTRL_PIN(224, "GPIO_224"),
333
+
PINCTRL_PIN(225, "GPIO_225"),
334
+
PINCTRL_PIN(226, "UFS_RESET"),
335
+
PINCTRL_PIN(227, "SDC2_CLK"),
336
+
PINCTRL_PIN(228, "SDC2_CMD"),
337
+
PINCTRL_PIN(229, "SDC2_DATA"),
338
+
};
339
+
340
+
#define DECLARE_MSM_GPIO_PINS(pin) \
341
+
static const unsigned int gpio##pin##_pins[] = { pin }
342
+
DECLARE_MSM_GPIO_PINS(0);
343
+
DECLARE_MSM_GPIO_PINS(1);
344
+
DECLARE_MSM_GPIO_PINS(2);
345
+
DECLARE_MSM_GPIO_PINS(3);
346
+
DECLARE_MSM_GPIO_PINS(4);
347
+
DECLARE_MSM_GPIO_PINS(5);
348
+
DECLARE_MSM_GPIO_PINS(6);
349
+
DECLARE_MSM_GPIO_PINS(7);
350
+
DECLARE_MSM_GPIO_PINS(8);
351
+
DECLARE_MSM_GPIO_PINS(9);
352
+
DECLARE_MSM_GPIO_PINS(10);
353
+
DECLARE_MSM_GPIO_PINS(11);
354
+
DECLARE_MSM_GPIO_PINS(12);
355
+
DECLARE_MSM_GPIO_PINS(13);
356
+
DECLARE_MSM_GPIO_PINS(14);
357
+
DECLARE_MSM_GPIO_PINS(15);
358
+
DECLARE_MSM_GPIO_PINS(16);
359
+
DECLARE_MSM_GPIO_PINS(17);
360
+
DECLARE_MSM_GPIO_PINS(18);
361
+
DECLARE_MSM_GPIO_PINS(19);
362
+
DECLARE_MSM_GPIO_PINS(20);
363
+
DECLARE_MSM_GPIO_PINS(21);
364
+
DECLARE_MSM_GPIO_PINS(22);
365
+
DECLARE_MSM_GPIO_PINS(23);
366
+
DECLARE_MSM_GPIO_PINS(24);
367
+
DECLARE_MSM_GPIO_PINS(25);
368
+
DECLARE_MSM_GPIO_PINS(26);
369
+
DECLARE_MSM_GPIO_PINS(27);
370
+
DECLARE_MSM_GPIO_PINS(28);
371
+
DECLARE_MSM_GPIO_PINS(29);
372
+
DECLARE_MSM_GPIO_PINS(30);
373
+
DECLARE_MSM_GPIO_PINS(31);
374
+
DECLARE_MSM_GPIO_PINS(32);
375
+
DECLARE_MSM_GPIO_PINS(33);
376
+
DECLARE_MSM_GPIO_PINS(34);
377
+
DECLARE_MSM_GPIO_PINS(35);
378
+
DECLARE_MSM_GPIO_PINS(36);
379
+
DECLARE_MSM_GPIO_PINS(37);
380
+
DECLARE_MSM_GPIO_PINS(38);
381
+
DECLARE_MSM_GPIO_PINS(39);
382
+
DECLARE_MSM_GPIO_PINS(40);
383
+
DECLARE_MSM_GPIO_PINS(41);
384
+
DECLARE_MSM_GPIO_PINS(42);
385
+
DECLARE_MSM_GPIO_PINS(43);
386
+
DECLARE_MSM_GPIO_PINS(44);
387
+
DECLARE_MSM_GPIO_PINS(45);
388
+
DECLARE_MSM_GPIO_PINS(46);
389
+
DECLARE_MSM_GPIO_PINS(47);
390
+
DECLARE_MSM_GPIO_PINS(48);
391
+
DECLARE_MSM_GPIO_PINS(49);
392
+
DECLARE_MSM_GPIO_PINS(50);
393
+
DECLARE_MSM_GPIO_PINS(51);
394
+
DECLARE_MSM_GPIO_PINS(52);
395
+
DECLARE_MSM_GPIO_PINS(53);
396
+
DECLARE_MSM_GPIO_PINS(54);
397
+
DECLARE_MSM_GPIO_PINS(55);
398
+
DECLARE_MSM_GPIO_PINS(56);
399
+
DECLARE_MSM_GPIO_PINS(57);
400
+
DECLARE_MSM_GPIO_PINS(58);
401
+
DECLARE_MSM_GPIO_PINS(59);
402
+
DECLARE_MSM_GPIO_PINS(60);
403
+
DECLARE_MSM_GPIO_PINS(61);
404
+
DECLARE_MSM_GPIO_PINS(62);
405
+
DECLARE_MSM_GPIO_PINS(63);
406
+
DECLARE_MSM_GPIO_PINS(64);
407
+
DECLARE_MSM_GPIO_PINS(65);
408
+
DECLARE_MSM_GPIO_PINS(66);
409
+
DECLARE_MSM_GPIO_PINS(67);
410
+
DECLARE_MSM_GPIO_PINS(68);
411
+
DECLARE_MSM_GPIO_PINS(69);
412
+
DECLARE_MSM_GPIO_PINS(70);
413
+
DECLARE_MSM_GPIO_PINS(71);
414
+
DECLARE_MSM_GPIO_PINS(72);
415
+
DECLARE_MSM_GPIO_PINS(73);
416
+
DECLARE_MSM_GPIO_PINS(74);
417
+
DECLARE_MSM_GPIO_PINS(75);
418
+
DECLARE_MSM_GPIO_PINS(76);
419
+
DECLARE_MSM_GPIO_PINS(77);
420
+
DECLARE_MSM_GPIO_PINS(78);
421
+
DECLARE_MSM_GPIO_PINS(79);
422
+
DECLARE_MSM_GPIO_PINS(80);
423
+
DECLARE_MSM_GPIO_PINS(81);
424
+
DECLARE_MSM_GPIO_PINS(82);
425
+
DECLARE_MSM_GPIO_PINS(83);
426
+
DECLARE_MSM_GPIO_PINS(84);
427
+
DECLARE_MSM_GPIO_PINS(85);
428
+
DECLARE_MSM_GPIO_PINS(86);
429
+
DECLARE_MSM_GPIO_PINS(87);
430
+
DECLARE_MSM_GPIO_PINS(88);
431
+
DECLARE_MSM_GPIO_PINS(89);
432
+
DECLARE_MSM_GPIO_PINS(90);
433
+
DECLARE_MSM_GPIO_PINS(91);
434
+
DECLARE_MSM_GPIO_PINS(92);
435
+
DECLARE_MSM_GPIO_PINS(93);
436
+
DECLARE_MSM_GPIO_PINS(94);
437
+
DECLARE_MSM_GPIO_PINS(95);
438
+
DECLARE_MSM_GPIO_PINS(96);
439
+
DECLARE_MSM_GPIO_PINS(97);
440
+
DECLARE_MSM_GPIO_PINS(98);
441
+
DECLARE_MSM_GPIO_PINS(99);
442
+
DECLARE_MSM_GPIO_PINS(100);
443
+
DECLARE_MSM_GPIO_PINS(101);
444
+
DECLARE_MSM_GPIO_PINS(102);
445
+
DECLARE_MSM_GPIO_PINS(103);
446
+
DECLARE_MSM_GPIO_PINS(104);
447
+
DECLARE_MSM_GPIO_PINS(105);
448
+
DECLARE_MSM_GPIO_PINS(106);
449
+
DECLARE_MSM_GPIO_PINS(107);
450
+
DECLARE_MSM_GPIO_PINS(108);
451
+
DECLARE_MSM_GPIO_PINS(109);
452
+
DECLARE_MSM_GPIO_PINS(110);
453
+
DECLARE_MSM_GPIO_PINS(111);
454
+
DECLARE_MSM_GPIO_PINS(112);
455
+
DECLARE_MSM_GPIO_PINS(113);
456
+
DECLARE_MSM_GPIO_PINS(114);
457
+
DECLARE_MSM_GPIO_PINS(115);
458
+
DECLARE_MSM_GPIO_PINS(116);
459
+
DECLARE_MSM_GPIO_PINS(117);
460
+
DECLARE_MSM_GPIO_PINS(118);
461
+
DECLARE_MSM_GPIO_PINS(119);
462
+
DECLARE_MSM_GPIO_PINS(120);
463
+
DECLARE_MSM_GPIO_PINS(121);
464
+
DECLARE_MSM_GPIO_PINS(122);
465
+
DECLARE_MSM_GPIO_PINS(123);
466
+
DECLARE_MSM_GPIO_PINS(124);
467
+
DECLARE_MSM_GPIO_PINS(125);
468
+
DECLARE_MSM_GPIO_PINS(126);
469
+
DECLARE_MSM_GPIO_PINS(127);
470
+
DECLARE_MSM_GPIO_PINS(128);
471
+
DECLARE_MSM_GPIO_PINS(129);
472
+
DECLARE_MSM_GPIO_PINS(130);
473
+
DECLARE_MSM_GPIO_PINS(131);
474
+
DECLARE_MSM_GPIO_PINS(132);
475
+
DECLARE_MSM_GPIO_PINS(133);
476
+
DECLARE_MSM_GPIO_PINS(134);
477
+
DECLARE_MSM_GPIO_PINS(135);
478
+
DECLARE_MSM_GPIO_PINS(136);
479
+
DECLARE_MSM_GPIO_PINS(137);
480
+
DECLARE_MSM_GPIO_PINS(138);
481
+
DECLARE_MSM_GPIO_PINS(139);
482
+
DECLARE_MSM_GPIO_PINS(140);
483
+
DECLARE_MSM_GPIO_PINS(141);
484
+
DECLARE_MSM_GPIO_PINS(142);
485
+
DECLARE_MSM_GPIO_PINS(143);
486
+
DECLARE_MSM_GPIO_PINS(144);
487
+
DECLARE_MSM_GPIO_PINS(145);
488
+
DECLARE_MSM_GPIO_PINS(146);
489
+
DECLARE_MSM_GPIO_PINS(147);
490
+
DECLARE_MSM_GPIO_PINS(148);
491
+
DECLARE_MSM_GPIO_PINS(149);
492
+
DECLARE_MSM_GPIO_PINS(150);
493
+
DECLARE_MSM_GPIO_PINS(151);
494
+
DECLARE_MSM_GPIO_PINS(152);
495
+
DECLARE_MSM_GPIO_PINS(153);
496
+
DECLARE_MSM_GPIO_PINS(154);
497
+
DECLARE_MSM_GPIO_PINS(155);
498
+
DECLARE_MSM_GPIO_PINS(156);
499
+
DECLARE_MSM_GPIO_PINS(157);
500
+
DECLARE_MSM_GPIO_PINS(158);
501
+
DECLARE_MSM_GPIO_PINS(159);
502
+
DECLARE_MSM_GPIO_PINS(160);
503
+
DECLARE_MSM_GPIO_PINS(161);
504
+
DECLARE_MSM_GPIO_PINS(162);
505
+
DECLARE_MSM_GPIO_PINS(163);
506
+
DECLARE_MSM_GPIO_PINS(164);
507
+
DECLARE_MSM_GPIO_PINS(165);
508
+
DECLARE_MSM_GPIO_PINS(166);
509
+
DECLARE_MSM_GPIO_PINS(167);
510
+
DECLARE_MSM_GPIO_PINS(168);
511
+
DECLARE_MSM_GPIO_PINS(169);
512
+
DECLARE_MSM_GPIO_PINS(170);
513
+
DECLARE_MSM_GPIO_PINS(171);
514
+
DECLARE_MSM_GPIO_PINS(172);
515
+
DECLARE_MSM_GPIO_PINS(173);
516
+
DECLARE_MSM_GPIO_PINS(174);
517
+
DECLARE_MSM_GPIO_PINS(175);
518
+
DECLARE_MSM_GPIO_PINS(176);
519
+
DECLARE_MSM_GPIO_PINS(177);
520
+
DECLARE_MSM_GPIO_PINS(178);
521
+
DECLARE_MSM_GPIO_PINS(179);
522
+
DECLARE_MSM_GPIO_PINS(180);
523
+
DECLARE_MSM_GPIO_PINS(181);
524
+
DECLARE_MSM_GPIO_PINS(182);
525
+
DECLARE_MSM_GPIO_PINS(183);
526
+
DECLARE_MSM_GPIO_PINS(184);
527
+
DECLARE_MSM_GPIO_PINS(185);
528
+
DECLARE_MSM_GPIO_PINS(186);
529
+
DECLARE_MSM_GPIO_PINS(187);
530
+
DECLARE_MSM_GPIO_PINS(188);
531
+
DECLARE_MSM_GPIO_PINS(189);
532
+
DECLARE_MSM_GPIO_PINS(190);
533
+
DECLARE_MSM_GPIO_PINS(191);
534
+
DECLARE_MSM_GPIO_PINS(192);
535
+
DECLARE_MSM_GPIO_PINS(193);
536
+
DECLARE_MSM_GPIO_PINS(194);
537
+
DECLARE_MSM_GPIO_PINS(195);
538
+
DECLARE_MSM_GPIO_PINS(196);
539
+
DECLARE_MSM_GPIO_PINS(197);
540
+
DECLARE_MSM_GPIO_PINS(198);
541
+
DECLARE_MSM_GPIO_PINS(199);
542
+
DECLARE_MSM_GPIO_PINS(200);
543
+
DECLARE_MSM_GPIO_PINS(201);
544
+
DECLARE_MSM_GPIO_PINS(202);
545
+
DECLARE_MSM_GPIO_PINS(203);
546
+
DECLARE_MSM_GPIO_PINS(204);
547
+
DECLARE_MSM_GPIO_PINS(205);
548
+
DECLARE_MSM_GPIO_PINS(206);
549
+
DECLARE_MSM_GPIO_PINS(207);
550
+
DECLARE_MSM_GPIO_PINS(208);
551
+
DECLARE_MSM_GPIO_PINS(209);
552
+
DECLARE_MSM_GPIO_PINS(210);
553
+
DECLARE_MSM_GPIO_PINS(211);
554
+
DECLARE_MSM_GPIO_PINS(212);
555
+
DECLARE_MSM_GPIO_PINS(213);
556
+
DECLARE_MSM_GPIO_PINS(214);
557
+
DECLARE_MSM_GPIO_PINS(215);
558
+
DECLARE_MSM_GPIO_PINS(216);
559
+
DECLARE_MSM_GPIO_PINS(217);
560
+
DECLARE_MSM_GPIO_PINS(218);
561
+
DECLARE_MSM_GPIO_PINS(219);
562
+
DECLARE_MSM_GPIO_PINS(220);
563
+
DECLARE_MSM_GPIO_PINS(221);
564
+
DECLARE_MSM_GPIO_PINS(222);
565
+
DECLARE_MSM_GPIO_PINS(223);
566
+
DECLARE_MSM_GPIO_PINS(224);
567
+
DECLARE_MSM_GPIO_PINS(225);
568
+
569
+
static const unsigned int ufs_reset_pins[] = { 226 };
570
+
static const unsigned int sdc2_clk_pins[] = { 227 };
571
+
static const unsigned int sdc2_cmd_pins[] = { 228 };
572
+
static const unsigned int sdc2_data_pins[] = { 229 };
573
+
574
+
enum hawi_functions {
575
+
msm_mux_gpio,
576
+
msm_mux_aoss_cti,
577
+
msm_mux_atest_char,
578
+
msm_mux_atest_usb,
579
+
msm_mux_audio_ext_mclk,
580
+
msm_mux_audio_ref_clk,
581
+
msm_mux_cam_mclk,
582
+
msm_mux_cci_async_in,
583
+
msm_mux_cci_i2c0,
584
+
msm_mux_cci_i2c1,
585
+
msm_mux_cci_i2c2,
586
+
msm_mux_cci_i2c3,
587
+
msm_mux_cci_i2c4,
588
+
msm_mux_cci_i2c5,
589
+
msm_mux_cci_timer,
590
+
msm_mux_coex_espmi,
591
+
msm_mux_coex_uart1_rx,
592
+
msm_mux_coex_uart1_tx,
593
+
msm_mux_dbg_out_clk,
594
+
msm_mux_ddr_bist,
595
+
msm_mux_ddr_pxi,
596
+
msm_mux_dp_hot,
597
+
msm_mux_egpio,
598
+
msm_mux_gcc_gp,
599
+
msm_mux_gnss_adc,
600
+
msm_mux_host_rst,
601
+
msm_mux_i2chub0_se0,
602
+
msm_mux_i2chub0_se1,
603
+
msm_mux_i2chub0_se2,
604
+
msm_mux_i2chub0_se3,
605
+
msm_mux_i2chub0_se4,
606
+
msm_mux_i2s0,
607
+
msm_mux_i2s1,
608
+
msm_mux_ibi_i3c,
609
+
msm_mux_jitter_bist,
610
+
msm_mux_mdp_esync0,
611
+
msm_mux_mdp_esync1,
612
+
msm_mux_mdp_esync2,
613
+
msm_mux_mdp_vsync,
614
+
msm_mux_mdp_vsync_e,
615
+
msm_mux_mdp_vsync_p,
616
+
msm_mux_mdp_vsync0_out,
617
+
msm_mux_mdp_vsync1_out,
618
+
msm_mux_mdp_vsync2_out,
619
+
msm_mux_mdp_vsync3_out,
620
+
msm_mux_mdp_vsync5_out,
621
+
msm_mux_modem_pps_in,
622
+
msm_mux_modem_pps_out,
623
+
msm_mux_nav_gpio,
624
+
msm_mux_nav_gpio0,
625
+
msm_mux_nav_gpio3,
626
+
msm_mux_nav_rffe,
627
+
msm_mux_pcie0_clk_req_n,
628
+
msm_mux_pcie0_rst_n,
629
+
msm_mux_pcie1_clk_req_n,
630
+
msm_mux_phase_flag,
631
+
msm_mux_pll_bist_sync,
632
+
msm_mux_pll_clk_aux,
633
+
msm_mux_qdss_cti,
634
+
msm_mux_qlink,
635
+
msm_mux_qspi,
636
+
msm_mux_qspi_clk,
637
+
msm_mux_qspi_cs,
638
+
msm_mux_qup1_se0,
639
+
msm_mux_qup1_se1,
640
+
msm_mux_qup1_se2,
641
+
msm_mux_qup1_se3,
642
+
msm_mux_qup1_se4,
643
+
msm_mux_qup1_se5,
644
+
msm_mux_qup1_se6,
645
+
msm_mux_qup1_se7,
646
+
msm_mux_qup2_se0,
647
+
msm_mux_qup2_se1,
648
+
msm_mux_qup2_se2,
649
+
msm_mux_qup2_se3,
650
+
msm_mux_qup2_se4_01,
651
+
msm_mux_qup2_se4_23,
652
+
msm_mux_qup3_se0_01,
653
+
msm_mux_qup3_se0_23,
654
+
msm_mux_qup3_se1,
655
+
msm_mux_qup3_se2,
656
+
msm_mux_qup3_se3,
657
+
msm_mux_qup3_se4,
658
+
msm_mux_qup3_se5,
659
+
msm_mux_qup4_se0,
660
+
msm_mux_qup4_se1,
661
+
msm_mux_qup4_se2,
662
+
msm_mux_qup4_se3_01,
663
+
msm_mux_qup4_se3_23,
664
+
msm_mux_qup4_se3_l3,
665
+
msm_mux_qup4_se4_01,
666
+
msm_mux_qup4_se4_23,
667
+
msm_mux_qup4_se4_l3,
668
+
msm_mux_rng_rosc,
669
+
msm_mux_sd_write_protect,
670
+
msm_mux_sdc4_clk,
671
+
msm_mux_sdc4_cmd,
672
+
msm_mux_sdc4_data,
673
+
msm_mux_sys_throttle,
674
+
msm_mux_tb_trig_sdc,
675
+
msm_mux_tmess_rng,
676
+
msm_mux_tsense_clm,
677
+
msm_mux_tsense_pwm,
678
+
msm_mux_uim0,
679
+
msm_mux_uim1,
680
+
msm_mux_usb0_hs,
681
+
msm_mux_usb_phy,
682
+
msm_mux_vfr,
683
+
msm_mux_vsense_trigger_mirnat,
684
+
msm_mux_wcn_sw_ctrl,
685
+
msm_mux__,
686
+
};
687
+
688
+
static const char *const gpio_groups[] = {
689
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
690
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
691
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
692
+
"gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
693
+
"gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
694
+
"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
695
+
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
696
+
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47",
697
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
698
+
"gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59",
699
+
"gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
700
+
"gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71",
701
+
"gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
702
+
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
703
+
"gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89",
704
+
"gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
705
+
"gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101",
706
+
"gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107",
707
+
"gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113",
708
+
"gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119",
709
+
"gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
710
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
711
+
"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
712
+
"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
713
+
"gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
714
+
"gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155",
715
+
"gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161",
716
+
"gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167",
717
+
"gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173",
718
+
"gpio174", "gpio175", "gpio176", "gpio177", "gpio178", "gpio179",
719
+
"gpio180", "gpio181", "gpio182", "gpio183", "gpio184", "gpio185",
720
+
"gpio186", "gpio187", "gpio188", "gpio189", "gpio190", "gpio191",
721
+
"gpio192", "gpio193", "gpio194", "gpio195", "gpio196", "gpio197",
722
+
"gpio198", "gpio199", "gpio200", "gpio201", "gpio202", "gpio203",
723
+
"gpio204", "gpio205", "gpio206", "gpio207", "gpio208", "gpio209",
724
+
"gpio210", "gpio211", "gpio212", "gpio213", "gpio214", "gpio215",
725
+
"gpio216", "gpio217", "gpio218", "gpio219", "gpio220", "gpio221",
726
+
"gpio222", "gpio223", "gpio224", "gpio225",
727
+
};
728
+
729
+
static const char *const aoss_cti_groups[] = {
730
+
"gpio74", "gpio75", "gpio76", "gpio77",
731
+
};
732
+
733
+
static const char *const atest_char_groups[] = {
734
+
"gpio126", "gpio127", "gpio128", "gpio129", "gpio133",
735
+
};
736
+
737
+
static const char *const atest_usb_groups[] = {
738
+
"gpio70", "gpio71", "gpio72", "gpio73", "gpio129",
739
+
};
740
+
741
+
static const char *const audio_ext_mclk_groups[] = {
742
+
"gpio120", "gpio121",
743
+
};
744
+
745
+
static const char *const audio_ref_clk_groups[] = {
746
+
"gpio120",
747
+
};
748
+
749
+
static const char *const cam_mclk_groups[] = {
750
+
"gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94",
751
+
"gpio95", "gpio96",
752
+
};
753
+
754
+
static const char *const cci_async_in_groups[] = {
755
+
"gpio15", "gpio109", "gpio110",
756
+
};
757
+
758
+
static const char *const cci_i2c0_groups[] = {
759
+
"gpio109", "gpio110",
760
+
};
761
+
762
+
static const char *const cci_i2c1_groups[] = {
763
+
"gpio111", "gpio112",
764
+
};
765
+
766
+
static const char *const cci_i2c2_groups[] = {
767
+
"gpio113", "gpio114",
768
+
};
769
+
770
+
static const char *const cci_i2c3_groups[] = {
771
+
"gpio107", "gpio160",
772
+
};
773
+
774
+
static const char *const cci_i2c4_groups[] = {
775
+
"gpio108", "gpio149",
776
+
};
777
+
778
+
static const char *const cci_i2c5_groups[] = {
779
+
"gpio115", "gpio116",
780
+
};
781
+
782
+
static const char *const cci_timer_groups[] = {
783
+
"gpio105", "gpio106", "gpio107", "gpio159", "gpio160",
784
+
};
785
+
786
+
static const char *const coex_espmi_groups[] = {
787
+
"gpio144", "gpio145",
788
+
};
789
+
790
+
static const char *const coex_uart1_rx_groups[] = {
791
+
"gpio144",
792
+
};
793
+
794
+
static const char *const coex_uart1_tx_groups[] = {
795
+
"gpio145",
796
+
};
797
+
798
+
static const char *const dbg_out_clk_groups[] = {
799
+
"gpio82",
800
+
};
801
+
802
+
static const char *const ddr_bist_groups[] = {
803
+
"gpio40", "gpio41", "gpio44", "gpio45",
804
+
};
805
+
806
+
static const char *const ddr_pxi_groups[] = {
807
+
"gpio43", "gpio44", "gpio45", "gpio46",
808
+
"gpio52", "gpio53", "gpio54", "gpio55",
809
+
};
810
+
811
+
static const char *const dp_hot_groups[] = {
812
+
"gpio47",
813
+
};
814
+
815
+
static const char *const egpio_groups[] = {
816
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
817
+
"gpio6", "gpio7", "gpio28", "gpio29", "gpio30", "gpio31",
818
+
"gpio48", "gpio49", "gpio50", "gpio51", "gpio163", "gpio164",
819
+
"gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
820
+
"gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
821
+
"gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182",
822
+
"gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188",
823
+
"gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194",
824
+
"gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200",
825
+
"gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206",
826
+
"gpio207", "gpio208", "gpio209", "gpio212", "gpio213", "gpio214",
827
+
"gpio215", "gpio216", "gpio217", "gpio218",
828
+
};
829
+
830
+
static const char *const gcc_gp_groups[] = {
831
+
"gpio86", "gpio87", "gpio130", "gpio131", "gpio132", "gpio158",
832
+
};
833
+
834
+
static const char *const gnss_adc_groups[] = {
835
+
"gpio40", "gpio41", "gpio42", "gpio77",
836
+
};
837
+
838
+
static const char *const host_rst_groups[] = {
839
+
"gpio106",
840
+
};
841
+
842
+
static const char *const i2chub0_se0_groups[] = {
843
+
"gpio66", "gpio67",
844
+
};
845
+
846
+
static const char *const i2chub0_se1_groups[] = {
847
+
"gpio78", "gpio79",
848
+
};
849
+
850
+
static const char *const i2chub0_se2_groups[] = {
851
+
"gpio68", "gpio69",
852
+
};
853
+
854
+
static const char *const i2chub0_se3_groups[] = {
855
+
"gpio70", "gpio71",
856
+
};
857
+
858
+
static const char *const i2chub0_se4_groups[] = {
859
+
"gpio72", "gpio73",
860
+
};
861
+
862
+
static const char *const i2s0_groups[] = {
863
+
"gpio122", "gpio123", "gpio124", "gpio125",
864
+
};
865
+
866
+
static const char *const i2s1_groups[] = {
867
+
"gpio117", "gpio118", "gpio119", "gpio120",
868
+
};
869
+
870
+
static const char *const ibi_i3c_groups[] = {
871
+
"gpio0", "gpio1", "gpio4", "gpio5", "gpio8", "gpio9",
872
+
"gpio12", "gpio13", "gpio28", "gpio29", "gpio32", "gpio33",
873
+
"gpio36", "gpio37", "gpio48", "gpio49", "gpio60", "gpio61",
874
+
};
875
+
876
+
static const char *const jitter_bist_groups[] = {
877
+
"gpio73",
878
+
};
879
+
880
+
static const char *const mdp_esync0_groups[] = {
881
+
"gpio88", "gpio100",
882
+
};
883
+
884
+
static const char *const mdp_esync1_groups[] = {
885
+
"gpio86", "gpio100",
886
+
};
887
+
888
+
static const char *const mdp_esync2_groups[] = {
889
+
"gpio87", "gpio97",
890
+
};
891
+
892
+
static const char *const mdp_vsync_groups[] = {
893
+
"gpio86", "gpio87", "gpio88", "gpio97",
894
+
};
895
+
896
+
static const char *const mdp_vsync_e_groups[] = {
897
+
"gpio98",
898
+
};
899
+
900
+
static const char *const mdp_vsync_p_groups[] = {
901
+
"gpio98",
902
+
};
903
+
904
+
static const char *const mdp_vsync0_out_groups[] = {
905
+
"gpio86",
906
+
};
907
+
908
+
static const char *const mdp_vsync1_out_groups[] = {
909
+
"gpio86",
910
+
};
911
+
912
+
static const char *const mdp_vsync2_out_groups[] = {
913
+
"gpio87",
914
+
};
915
+
916
+
static const char *const mdp_vsync3_out_groups[] = {
917
+
"gpio87",
918
+
};
919
+
920
+
static const char *const mdp_vsync5_out_groups[] = {
921
+
"gpio87",
922
+
};
923
+
924
+
static const char *const modem_pps_in_groups[] = {
925
+
"gpio151",
926
+
};
927
+
928
+
static const char *const modem_pps_out_groups[] = {
929
+
"gpio151",
930
+
};
931
+
932
+
static const char *const nav_gpio_groups[] = {
933
+
"gpio146", "gpio147", "gpio148", "gpio151",
934
+
};
935
+
936
+
static const char *const nav_gpio0_groups[] = {
937
+
"gpio150",
938
+
};
939
+
940
+
static const char *const nav_gpio3_groups[] = {
941
+
"gpio150",
942
+
};
943
+
944
+
static const char *const nav_rffe_groups[] = {
945
+
"gpio134", "gpio135", "gpio138", "gpio139",
946
+
};
947
+
948
+
static const char *const pcie0_clk_req_n_groups[] = {
949
+
"gpio103",
950
+
};
951
+
952
+
static const char *const pcie0_rst_n_groups[] = {
953
+
"gpio102",
954
+
};
955
+
956
+
static const char *const pcie1_clk_req_n_groups[] = {
957
+
"gpio221",
958
+
};
959
+
960
+
static const char *const phase_flag_groups[] = {
961
+
"gpio117", "gpio118", "gpio119", "gpio123", "gpio124", "gpio125",
962
+
"gpio169", "gpio170", "gpio171", "gpio172", "gpio173", "gpio175",
963
+
"gpio176", "gpio179", "gpio180", "gpio181", "gpio184", "gpio185",
964
+
"gpio192", "gpio196", "gpio197", "gpio198", "gpio199", "gpio204",
965
+
"gpio206", "gpio207", "gpio208", "gpio210", "gpio211", "gpio214",
966
+
"gpio215", "gpio216",
967
+
};
968
+
969
+
static const char *const pll_bist_sync_groups[] = {
970
+
"gpio104",
971
+
};
972
+
973
+
static const char *const pll_clk_aux_groups[] = {
974
+
"gpio94",
975
+
};
976
+
977
+
static const char *const qdss_cti_groups[] = {
978
+
"gpio27", "gpio31", "gpio72", "gpio73", "gpio82", "gpio83",
979
+
"gpio152", "gpio158",
980
+
};
981
+
982
+
static const char *const qlink_groups[] = {
983
+
"gpio152", "gpio153", "gpio154",
984
+
};
985
+
986
+
static const char *const qspi_groups[] = {
987
+
"gpio80", "gpio81", "gpio82", "gpio147",
988
+
};
989
+
990
+
static const char *const qspi_clk_groups[] = {
991
+
"gpio83",
992
+
};
993
+
994
+
static const char *const qspi_cs_groups[] = {
995
+
"gpio146", "gpio148",
996
+
};
997
+
998
+
static const char *const qup1_se0_groups[] = {
999
+
"gpio80", "gpio81", "gpio82", "gpio83",
1000
+
};
1001
+
1002
+
static const char *const qup1_se1_groups[] = {
1003
+
"gpio74", "gpio75", "gpio76", "gpio77",
1004
+
};
1005
+
1006
+
static const char *const qup1_se2_groups[] = {
1007
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio130", "gpio131", "gpio132",
1008
+
};
1009
+
1010
+
static const char *const qup1_se3_groups[] = {
1011
+
"gpio44", "gpio45", "gpio46", "gpio47",
1012
+
};
1013
+
1014
+
static const char *const qup1_se4_groups[] = {
1015
+
"gpio36", "gpio37", "gpio38", "gpio39",
1016
+
};
1017
+
1018
+
static const char *const qup1_se5_groups[] = {
1019
+
"gpio52", "gpio53", "gpio54", "gpio55",
1020
+
};
1021
+
1022
+
static const char *const qup1_se6_groups[] = {
1023
+
"gpio56", "gpio57", "gpio58", "gpio59",
1024
+
};
1025
+
1026
+
static const char *const qup1_se7_groups[] = {
1027
+
"gpio60", "gpio61", "gpio62", "gpio63",
1028
+
};
1029
+
1030
+
static const char *const qup2_se0_groups[] = {
1031
+
"gpio0", "gpio1", "gpio2", "gpio3",
1032
+
};
1033
+
1034
+
static const char *const qup2_se1_groups[] = {
1035
+
"gpio4", "gpio5", "gpio6", "gpio7",
1036
+
};
1037
+
1038
+
static const char *const qup2_se2_groups[] = {
1039
+
"gpio117", "gpio118", "gpio119", "gpio120",
1040
+
};
1041
+
1042
+
static const char *const qup2_se3_groups[] = {
1043
+
"gpio97", "gpio122", "gpio123", "gpio124", "gpio125",
1044
+
};
1045
+
1046
+
static const char *const qup2_se4_01_groups[] = {
1047
+
"gpio208", "gpio209",
1048
+
};
1049
+
1050
+
static const char *const qup2_se4_23_groups[] = {
1051
+
"gpio208", "gpio209",
1052
+
};
1053
+
1054
+
static const char *const qup3_se0_01_groups[] = {
1055
+
"gpio64", "gpio65",
1056
+
};
1057
+
1058
+
static const char *const qup3_se0_23_groups[] = {
1059
+
"gpio64", "gpio65",
1060
+
};
1061
+
1062
+
static const char *const qup3_se1_groups[] = {
1063
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio15",
1064
+
};
1065
+
1066
+
static const char *const qup3_se2_groups[] = {
1067
+
"gpio12", "gpio13", "gpio14", "gpio15",
1068
+
};
1069
+
1070
+
static const char *const qup3_se3_groups[] = {
1071
+
"gpio16", "gpio17", "gpio18", "gpio19",
1072
+
};
1073
+
1074
+
static const char *const qup3_se4_groups[] = {
1075
+
"gpio20", "gpio21", "gpio22", "gpio23",
1076
+
};
1077
+
1078
+
static const char *const qup3_se5_groups[] = {
1079
+
"gpio24", "gpio25", "gpio26", "gpio27",
1080
+
};
1081
+
1082
+
static const char *const qup4_se0_groups[] = {
1083
+
"gpio48", "gpio49", "gpio50", "gpio51",
1084
+
};
1085
+
1086
+
static const char *const qup4_se1_groups[] = {
1087
+
"gpio28", "gpio29", "gpio30", "gpio31",
1088
+
};
1089
+
1090
+
static const char *const qup4_se2_groups[] = {
1091
+
"gpio32", "gpio33", "gpio34", "gpio35",
1092
+
};
1093
+
1094
+
static const char *const qup4_se3_01_groups[] = {
1095
+
"gpio84", "gpio121",
1096
+
};
1097
+
1098
+
static const char *const qup4_se3_23_groups[] = {
1099
+
"gpio84", "gpio121",
1100
+
};
1101
+
1102
+
static const char *const qup4_se3_l3_groups[] = {
1103
+
"gpio98",
1104
+
};
1105
+
1106
+
static const char *const qup4_se4_01_groups[] = {
1107
+
"gpio161", "gpio162",
1108
+
};
1109
+
1110
+
static const char *const qup4_se4_23_groups[] = {
1111
+
"gpio161", "gpio162",
1112
+
};
1113
+
1114
+
static const char *const qup4_se4_l3_groups[] = {
1115
+
"gpio88",
1116
+
};
1117
+
1118
+
static const char *const rng_rosc_groups[] = {
1119
+
"gpio64", "gpio65", "gpio66", "gpio84",
1120
+
};
1121
+
1122
+
static const char *const sd_write_protect_groups[] = {
1123
+
"gpio85",
1124
+
};
1125
+
1126
+
static const char *const sdc4_clk_groups[] = {
1127
+
"gpio83",
1128
+
};
1129
+
1130
+
static const char *const sdc4_cmd_groups[] = {
1131
+
"gpio148",
1132
+
};
1133
+
1134
+
static const char *const sdc4_data_groups[] = {
1135
+
"gpio80", "gpio81", "gpio82", "gpio147",
1136
+
};
1137
+
1138
+
static const char *const sys_throttle_groups[] = {
1139
+
"gpio99",
1140
+
};
1141
+
1142
+
static const char *const tb_trig_sdc_groups[] = {
1143
+
"gpio88", "gpio146",
1144
+
};
1145
+
1146
+
static const char *const tmess_rng_groups[] = {
1147
+
"gpio64", "gpio65", "gpio66", "gpio84",
1148
+
};
1149
+
1150
+
static const char *const tsense_clm_groups[] = {
1151
+
"gpio10", "gpio87", "gpio97", "gpio99", "gpio105", "gpio106",
1152
+
"gpio159",
1153
+
};
1154
+
1155
+
static const char *const tsense_pwm_groups[] = {
1156
+
"gpio10", "gpio87", "gpio97", "gpio99", "gpio223", "gpio224",
1157
+
"gpio225",
1158
+
};
1159
+
1160
+
static const char *const uim0_groups[] = {
1161
+
"gpio126", "gpio127", "gpio128", "gpio129",
1162
+
};
1163
+
1164
+
static const char *const uim1_groups[] = {
1165
+
"gpio36", "gpio37", "gpio39", "gpio54", "gpio55", "gpio56",
1166
+
"gpio70", "gpio71", "gpio72", "gpio130", "gpio131", "gpio132",
1167
+
"gpio133",
1168
+
};
1169
+
1170
+
static const char *const usb0_hs_groups[] = {
1171
+
"gpio79",
1172
+
};
1173
+
1174
+
static const char *const usb_phy_groups[] = {
1175
+
"gpio59", "gpio60",
1176
+
};
1177
+
1178
+
static const char *const vfr_groups[] = {
1179
+
"gpio146", "gpio151",
1180
+
};
1181
+
1182
+
static const char *const vsense_trigger_mirnat_groups[] = {
1183
+
"gpio59",
1184
+
};
1185
+
1186
+
static const char *const wcn_sw_ctrl_groups[] = {
1187
+
"gpio18", "gpio19", "gpio155", "gpio156",
1188
+
};
1189
+
1190
+
static const struct pinfunction hawi_functions[] = {
1191
+
MSM_GPIO_PIN_FUNCTION(gpio),
1192
+
MSM_PIN_FUNCTION(aoss_cti),
1193
+
MSM_PIN_FUNCTION(atest_char),
1194
+
MSM_PIN_FUNCTION(atest_usb),
1195
+
MSM_PIN_FUNCTION(audio_ext_mclk),
1196
+
MSM_PIN_FUNCTION(audio_ref_clk),
1197
+
MSM_PIN_FUNCTION(cam_mclk),
1198
+
MSM_PIN_FUNCTION(cci_async_in),
1199
+
MSM_PIN_FUNCTION(cci_i2c0),
1200
+
MSM_PIN_FUNCTION(cci_i2c1),
1201
+
MSM_PIN_FUNCTION(cci_i2c2),
1202
+
MSM_PIN_FUNCTION(cci_i2c3),
1203
+
MSM_PIN_FUNCTION(cci_i2c4),
1204
+
MSM_PIN_FUNCTION(cci_i2c5),
1205
+
MSM_PIN_FUNCTION(cci_timer),
1206
+
MSM_PIN_FUNCTION(coex_espmi),
1207
+
MSM_PIN_FUNCTION(coex_uart1_rx),
1208
+
MSM_PIN_FUNCTION(coex_uart1_tx),
1209
+
MSM_PIN_FUNCTION(dbg_out_clk),
1210
+
MSM_PIN_FUNCTION(ddr_bist),
1211
+
MSM_PIN_FUNCTION(ddr_pxi),
1212
+
MSM_PIN_FUNCTION(dp_hot),
1213
+
MSM_PIN_FUNCTION(egpio),
1214
+
MSM_PIN_FUNCTION(gcc_gp),
1215
+
MSM_PIN_FUNCTION(gnss_adc),
1216
+
MSM_PIN_FUNCTION(host_rst),
1217
+
MSM_PIN_FUNCTION(i2chub0_se0),
1218
+
MSM_PIN_FUNCTION(i2chub0_se1),
1219
+
MSM_PIN_FUNCTION(i2chub0_se2),
1220
+
MSM_PIN_FUNCTION(i2chub0_se3),
1221
+
MSM_PIN_FUNCTION(i2chub0_se4),
1222
+
MSM_PIN_FUNCTION(i2s0),
1223
+
MSM_PIN_FUNCTION(i2s1),
1224
+
MSM_PIN_FUNCTION(ibi_i3c),
1225
+
MSM_PIN_FUNCTION(jitter_bist),
1226
+
MSM_PIN_FUNCTION(mdp_esync0),
1227
+
MSM_PIN_FUNCTION(mdp_esync1),
1228
+
MSM_PIN_FUNCTION(mdp_esync2),
1229
+
MSM_PIN_FUNCTION(mdp_vsync),
1230
+
MSM_PIN_FUNCTION(mdp_vsync_e),
1231
+
MSM_PIN_FUNCTION(mdp_vsync_p),
1232
+
MSM_PIN_FUNCTION(mdp_vsync0_out),
1233
+
MSM_PIN_FUNCTION(mdp_vsync1_out),
1234
+
MSM_PIN_FUNCTION(mdp_vsync2_out),
1235
+
MSM_PIN_FUNCTION(mdp_vsync3_out),
1236
+
MSM_PIN_FUNCTION(mdp_vsync5_out),
1237
+
MSM_PIN_FUNCTION(modem_pps_in),
1238
+
MSM_PIN_FUNCTION(modem_pps_out),
1239
+
MSM_PIN_FUNCTION(nav_gpio),
1240
+
MSM_PIN_FUNCTION(nav_gpio0),
1241
+
MSM_PIN_FUNCTION(nav_gpio3),
1242
+
MSM_PIN_FUNCTION(nav_rffe),
1243
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
1244
+
MSM_PIN_FUNCTION(pcie0_rst_n),
1245
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
1246
+
MSM_PIN_FUNCTION(phase_flag),
1247
+
MSM_PIN_FUNCTION(pll_bist_sync),
1248
+
MSM_PIN_FUNCTION(pll_clk_aux),
1249
+
MSM_PIN_FUNCTION(qdss_cti),
1250
+
MSM_PIN_FUNCTION(qlink),
1251
+
MSM_PIN_FUNCTION(qspi),
1252
+
MSM_PIN_FUNCTION(qspi_clk),
1253
+
MSM_PIN_FUNCTION(qspi_cs),
1254
+
MSM_PIN_FUNCTION(qup1_se0),
1255
+
MSM_PIN_FUNCTION(qup1_se1),
1256
+
MSM_PIN_FUNCTION(qup1_se2),
1257
+
MSM_PIN_FUNCTION(qup1_se3),
1258
+
MSM_PIN_FUNCTION(qup1_se4),
1259
+
MSM_PIN_FUNCTION(qup1_se5),
1260
+
MSM_PIN_FUNCTION(qup1_se6),
1261
+
MSM_PIN_FUNCTION(qup1_se7),
1262
+
MSM_PIN_FUNCTION(qup2_se0),
1263
+
MSM_PIN_FUNCTION(qup2_se1),
1264
+
MSM_PIN_FUNCTION(qup2_se2),
1265
+
MSM_PIN_FUNCTION(qup2_se3),
1266
+
MSM_PIN_FUNCTION(qup2_se4_01),
1267
+
MSM_PIN_FUNCTION(qup2_se4_23),
1268
+
MSM_PIN_FUNCTION(qup3_se0_01),
1269
+
MSM_PIN_FUNCTION(qup3_se0_23),
1270
+
MSM_PIN_FUNCTION(qup3_se1),
1271
+
MSM_PIN_FUNCTION(qup3_se2),
1272
+
MSM_PIN_FUNCTION(qup3_se3),
1273
+
MSM_PIN_FUNCTION(qup3_se4),
1274
+
MSM_PIN_FUNCTION(qup3_se5),
1275
+
MSM_PIN_FUNCTION(qup4_se0),
1276
+
MSM_PIN_FUNCTION(qup4_se1),
1277
+
MSM_PIN_FUNCTION(qup4_se2),
1278
+
MSM_PIN_FUNCTION(qup4_se3_01),
1279
+
MSM_PIN_FUNCTION(qup4_se3_23),
1280
+
MSM_PIN_FUNCTION(qup4_se3_l3),
1281
+
MSM_PIN_FUNCTION(qup4_se4_01),
1282
+
MSM_PIN_FUNCTION(qup4_se4_23),
1283
+
MSM_PIN_FUNCTION(qup4_se4_l3),
1284
+
MSM_PIN_FUNCTION(rng_rosc),
1285
+
MSM_PIN_FUNCTION(sd_write_protect),
1286
+
MSM_PIN_FUNCTION(sdc4_clk),
1287
+
MSM_PIN_FUNCTION(sdc4_cmd),
1288
+
MSM_PIN_FUNCTION(sdc4_data),
1289
+
MSM_PIN_FUNCTION(sys_throttle),
1290
+
MSM_PIN_FUNCTION(tb_trig_sdc),
1291
+
MSM_PIN_FUNCTION(tmess_rng),
1292
+
MSM_PIN_FUNCTION(tsense_clm),
1293
+
MSM_PIN_FUNCTION(tsense_pwm),
1294
+
MSM_PIN_FUNCTION(uim0),
1295
+
MSM_PIN_FUNCTION(uim1),
1296
+
MSM_PIN_FUNCTION(usb0_hs),
1297
+
MSM_PIN_FUNCTION(usb_phy),
1298
+
MSM_PIN_FUNCTION(vfr),
1299
+
MSM_PIN_FUNCTION(vsense_trigger_mirnat),
1300
+
MSM_PIN_FUNCTION(wcn_sw_ctrl),
1301
+
};
1302
+
1303
+
/*
1304
+
* Every pin is maintained as a single group, and missing or non-existing pin
1305
+
* would be maintained as dummy group to synchronize pin group index with
1306
+
* pin descriptor registered with pinctrl core.
1307
+
* Clients would not be able to request these dummy pin groups.
1308
+
*/
1309
+
static const struct msm_pingroup hawi_groups[] = {
1310
+
[0] = PINGROUP(0, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1311
+
[1] = PINGROUP(1, qup2_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1312
+
[2] = PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
1313
+
[3] = PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, egpio),
1314
+
[4] = PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1315
+
[5] = PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1316
+
[6] = PINGROUP(6, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
1317
+
[7] = PINGROUP(7, qup2_se1, _, _, _, _, _, _, _, _, _, egpio),
1318
+
[8] = PINGROUP(8, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1319
+
[9] = PINGROUP(9, qup3_se1, ibi_i3c, _, _, _, _, _, _, _, _, _),
1320
+
[10] = PINGROUP(10, qup3_se1, _, tsense_clm, tsense_pwm, _, _, _, _, _, _, _),
1321
+
[11] = PINGROUP(11, qup3_se1, _, _, _, _, _, _, _, _, _, _),
1322
+
[12] = PINGROUP(12, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
1323
+
[13] = PINGROUP(13, qup3_se2, ibi_i3c, qup3_se1, _, _, _, _, _, _, _, _),
1324
+
[14] = PINGROUP(14, qup3_se2, _, _, _, _, _, _, _, _, _, _),
1325
+
[15] = PINGROUP(15, qup3_se2, cci_async_in, qup3_se1, _, _, _, _, _, _, _, _),
1326
+
[16] = PINGROUP(16, qup3_se3, _, _, _, _, _, _, _, _, _, _),
1327
+
[17] = PINGROUP(17, qup3_se3, _, _, _, _, _, _, _, _, _, _),
1328
+
[18] = PINGROUP(18, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
1329
+
[19] = PINGROUP(19, wcn_sw_ctrl, qup3_se3, _, _, _, _, _, _, _, _, _),
1330
+
[20] = PINGROUP(20, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1331
+
[21] = PINGROUP(21, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1332
+
[22] = PINGROUP(22, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1333
+
[23] = PINGROUP(23, qup3_se4, _, _, _, _, _, _, _, _, _, _),
1334
+
[24] = PINGROUP(24, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1335
+
[25] = PINGROUP(25, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1336
+
[26] = PINGROUP(26, qup3_se5, _, _, _, _, _, _, _, _, _, _),
1337
+
[27] = PINGROUP(27, qup3_se5, qdss_cti, _, _, _, _, _, _, _, _, _),
1338
+
[28] = PINGROUP(28, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1339
+
[29] = PINGROUP(29, qup4_se1, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1340
+
[30] = PINGROUP(30, qup4_se1, _, _, _, _, _, _, _, _, _, egpio),
1341
+
[31] = PINGROUP(31, qup4_se1, qdss_cti, _, _, _, _, _, _, _, _, egpio),
1342
+
[32] = PINGROUP(32, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
1343
+
[33] = PINGROUP(33, qup4_se2, ibi_i3c, _, _, _, _, _, _, _, _, _),
1344
+
[34] = PINGROUP(34, qup4_se2, _, _, _, _, _, _, _, _, _, _),
1345
+
[35] = PINGROUP(35, qup4_se2, _, _, _, _, _, _, _, _, _, _),
1346
+
[36] = PINGROUP(36, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
1347
+
[37] = PINGROUP(37, qup1_se4, uim1, ibi_i3c, _, _, _, _, _, _, _, _),
1348
+
[38] = PINGROUP(38, qup1_se4, _, _, _, _, _, _, _, _, _, _),
1349
+
[39] = PINGROUP(39, qup1_se4, uim1, _, _, _, _, _, _, _, _, _),
1350
+
[40] = PINGROUP(40, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
1351
+
[41] = PINGROUP(41, qup1_se2, ddr_bist, _, gnss_adc, _, _, _, _, _, _, _),
1352
+
[42] = PINGROUP(42, qup1_se2, gnss_adc, _, _, _, _, _, _, _, _, _),
1353
+
[43] = PINGROUP(43, qup1_se2, _, ddr_pxi, _, _, _, _, _, _, _, _),
1354
+
[44] = PINGROUP(44, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
1355
+
[45] = PINGROUP(45, qup1_se3, ddr_bist, ddr_pxi, _, _, _, _, _, _, _, _),
1356
+
[46] = PINGROUP(46, qup1_se3, ddr_pxi, _, _, _, _, _, _, _, _, _),
1357
+
[47] = PINGROUP(47, qup1_se3, dp_hot, _, _, _, _, _, _, _, _, _),
1358
+
[48] = PINGROUP(48, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1359
+
[49] = PINGROUP(49, qup4_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),
1360
+
[50] = PINGROUP(50, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
1361
+
[51] = PINGROUP(51, qup4_se0, _, _, _, _, _, _, _, _, _, egpio),
1362
+
[52] = PINGROUP(52, qup1_se5, ddr_pxi, _, _, _, _, _, _, _, _, _),
1363
+
[53] = PINGROUP(53, qup1_se5, _, ddr_pxi, _, _, _, _, _, _, _, _),
1364
+
[54] = PINGROUP(54, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
1365
+
[55] = PINGROUP(55, qup1_se5, uim1, ddr_pxi, _, _, _, _, _, _, _, _),
1366
+
[56] = PINGROUP(56, qup1_se6, uim1, _, _, _, _, _, _, _, _, _),
1367
+
[57] = PINGROUP(57, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1368
+
[58] = PINGROUP(58, qup1_se6, _, _, _, _, _, _, _, _, _, _),
1369
+
[59] = PINGROUP(59, qup1_se6, usb_phy, vsense_trigger_mirnat, _, _, _, _, _, _, _, _),
1370
+
[60] = PINGROUP(60, qup1_se7, usb_phy, ibi_i3c, _, _, _, _, _, _, _, _),
1371
+
[61] = PINGROUP(61, qup1_se7, ibi_i3c, _, _, _, _, _, _, _, _, _),
1372
+
[62] = PINGROUP(62, qup1_se7, _, _, _, _, _, _, _, _, _, _),
1373
+
[63] = PINGROUP(63, qup1_se7, _, _, _, _, _, _, _, _, _, _),
1374
+
[64] = PINGROUP(64, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1375
+
[65] = PINGROUP(65, qup3_se0_01, qup3_se0_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1376
+
[66] = PINGROUP(66, i2chub0_se0, rng_rosc, tmess_rng, _, _, _, _, _, _, _, _),
1377
+
[67] = PINGROUP(67, i2chub0_se0, _, _, _, _, _, _, _, _, _, _),
1378
+
[68] = PINGROUP(68, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
1379
+
[69] = PINGROUP(69, i2chub0_se2, _, _, _, _, _, _, _, _, _, _),
1380
+
[70] = PINGROUP(70, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
1381
+
[71] = PINGROUP(71, i2chub0_se3, uim1, _, atest_usb, _, _, _, _, _, _, _),
1382
+
[72] = PINGROUP(72, i2chub0_se4, uim1, qdss_cti, _, atest_usb, _, _, _, _, _, _),
1383
+
[73] = PINGROUP(73, i2chub0_se4, qdss_cti, jitter_bist, atest_usb, _, _, _, _, _, _, _),
1384
+
[74] = PINGROUP(74, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1385
+
[75] = PINGROUP(75, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1386
+
[76] = PINGROUP(76, qup1_se1, aoss_cti, _, _, _, _, _, _, _, _, _),
1387
+
[77] = PINGROUP(77, qup1_se1, aoss_cti, gnss_adc, _, _, _, _, _, _, _, _),
1388
+
[78] = PINGROUP(78, i2chub0_se1, _, _, _, _, _, _, _, _, _, _),
1389
+
[79] = PINGROUP(79, i2chub0_se1, usb0_hs, _, _, _, _, _, _, _, _, _),
1390
+
[80] = PINGROUP(80, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
1391
+
[81] = PINGROUP(81, qup1_se0, sdc4_data, qspi, _, _, _, _, _, _, _, _),
1392
+
[82] = PINGROUP(82, qup1_se0, sdc4_data, qdss_cti, qspi, dbg_out_clk, _, _, _, _, _, _),
1393
+
[83] = PINGROUP(83, qup1_se0, sdc4_clk, qdss_cti, qspi_clk, _, _, _, _, _, _, _),
1394
+
[84] = PINGROUP(84, qup4_se3_01, qup4_se3_23, rng_rosc, tmess_rng, _, _, _, _, _, _, _),
1395
+
[85] = PINGROUP(85, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
1396
+
[86] = PINGROUP(86, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_esync1, gcc_gp,
1397
+
_, _, _, _, _, _),
1398
+
[87] = PINGROUP(87, mdp_vsync, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
1399
+
mdp_esync2, gcc_gp, _, tsense_clm, tsense_pwm, _, _),
1400
+
[88] = PINGROUP(88, mdp_esync0, mdp_vsync, qup4_se4_l3, tb_trig_sdc, _, _, _, _, _, _, _),
1401
+
[89] = PINGROUP(89, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1402
+
[90] = PINGROUP(90, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1403
+
[91] = PINGROUP(91, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1404
+
[92] = PINGROUP(92, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1405
+
[93] = PINGROUP(93, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1406
+
[94] = PINGROUP(94, cam_mclk, pll_clk_aux, _, _, _, _, _, _, _, _, _),
1407
+
[95] = PINGROUP(95, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1408
+
[96] = PINGROUP(96, cam_mclk, _, _, _, _, _, _, _, _, _, _),
1409
+
[97] = PINGROUP(97, mdp_esync2, qup2_se3, mdp_vsync, tsense_clm, tsense_pwm, _, _,
1410
+
_, _, _, _),
1411
+
[98] = PINGROUP(98, mdp_vsync_e, qup4_se3_l3, mdp_vsync_p, _, _, _, _, _, _, _, _),
1412
+
[99] = PINGROUP(99, sys_throttle, tsense_clm, tsense_pwm, _, _, _, _, _, _, _, _),
1413
+
[100] = PINGROUP(100, mdp_esync1, mdp_esync0, _, _, _, _, _, _, _, _, _),
1414
+
[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
1415
+
[102] = PINGROUP(102, pcie0_rst_n, _, _, _, _, _, _, _, _, _, _),
1416
+
[103] = PINGROUP(103, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1417
+
[104] = PINGROUP(104, pll_bist_sync, _, _, _, _, _, _, _, _, _, _),
1418
+
[105] = PINGROUP(105, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
1419
+
[106] = PINGROUP(106, host_rst, cci_timer, tsense_clm, _, _, _, _, _, _, _, _),
1420
+
[107] = PINGROUP(107, cci_i2c3, cci_timer, _, _, _, _, _, _, _, _, _),
1421
+
[108] = PINGROUP(108, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
1422
+
[109] = PINGROUP(109, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
1423
+
[110] = PINGROUP(110, cci_i2c0, cci_async_in, _, _, _, _, _, _, _, _, _),
1424
+
[111] = PINGROUP(111, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1425
+
[112] = PINGROUP(112, cci_i2c1, _, _, _, _, _, _, _, _, _, _),
1426
+
[113] = PINGROUP(113, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
1427
+
[114] = PINGROUP(114, cci_i2c2, _, _, _, _, _, _, _, _, _, _),
1428
+
[115] = PINGROUP(115, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
1429
+
[116] = PINGROUP(116, cci_i2c5, _, _, _, _, _, _, _, _, _, _),
1430
+
[117] = PINGROUP(117, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1431
+
[118] = PINGROUP(118, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1432
+
[119] = PINGROUP(119, i2s1, qup2_se2, phase_flag, _, _, _, _, _, _, _, _),
1433
+
[120] = PINGROUP(120, i2s1, qup2_se2, audio_ext_mclk, audio_ref_clk, _, _,
1434
+
_, _, _, _, _),
1435
+
[121] = PINGROUP(121, audio_ext_mclk, qup4_se3_01, qup4_se3_23, _, _, _, _, _, _, _, _),
1436
+
[122] = PINGROUP(122, i2s0, qup2_se3, _, _, _, _, _, _, _, _, _),
1437
+
[123] = PINGROUP(123, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
1438
+
[124] = PINGROUP(124, i2s0, qup2_se3, _, phase_flag, _, _, _, _, _, _, _),
1439
+
[125] = PINGROUP(125, i2s0, qup2_se3, phase_flag, _, _, _, _, _, _, _, _),
1440
+
[126] = PINGROUP(126, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1441
+
[127] = PINGROUP(127, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1442
+
[128] = PINGROUP(128, uim0, atest_char, _, _, _, _, _, _, _, _, _),
1443
+
[129] = PINGROUP(129, uim0, atest_usb, atest_char, _, _, _, _, _, _, _, _),
1444
+
[130] = PINGROUP(130, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1445
+
[131] = PINGROUP(131, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1446
+
[132] = PINGROUP(132, uim1, qup1_se2, gcc_gp, _, _, _, _, _, _, _, _),
1447
+
[133] = PINGROUP(133, uim1, atest_char, _, _, _, _, _, _, _, _, _),
1448
+
[134] = PINGROUP(134, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1449
+
[135] = PINGROUP(135, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1450
+
[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _),
1451
+
[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _),
1452
+
[138] = PINGROUP(138, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1453
+
[139] = PINGROUP(139, _, _, nav_rffe, _, _, _, _, _, _, _, _),
1454
+
[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _, _, _),
1455
+
[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _, _, _),
1456
+
[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _, _, _),
1457
+
[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _, _, _),
1458
+
[144] = PINGROUP(144, coex_uart1_rx, coex_espmi, _, _, _, _, _, _, _, _, _),
1459
+
[145] = PINGROUP(145, coex_uart1_tx, coex_espmi, _, _, _, _, _, _, _, _, _),
1460
+
[146] = PINGROUP(146, _, vfr, nav_gpio, tb_trig_sdc, qspi_cs, _, _, _, _, _, _),
1461
+
[147] = PINGROUP(147, _, nav_gpio, sdc4_data, qspi, _, _, _, _, _, _, _),
1462
+
[148] = PINGROUP(148, nav_gpio, _, sdc4_cmd, qspi_cs, _, _, _, _, _, _, _),
1463
+
[149] = PINGROUP(149, cci_i2c4, _, _, _, _, _, _, _, _, _, _),
1464
+
[150] = PINGROUP(150, nav_gpio0, nav_gpio3, _, _, _, _, _, _, _, _, _),
1465
+
[151] = PINGROUP(151, nav_gpio, vfr, modem_pps_in, modem_pps_out, _, _, _, _, _, _, _),
1466
+
[152] = PINGROUP(152, qlink, qdss_cti, _, _, _, _, _, _, _, _, _),
1467
+
[153] = PINGROUP(153, qlink, _, _, _, _, _, _, _, _, _, _),
1468
+
[154] = PINGROUP(154, qlink, _, _, _, _, _, _, _, _, _, _),
1469
+
[155] = PINGROUP(155, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
1470
+
[156] = PINGROUP(156, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),
1471
+
[157] = PINGROUP(157, _, _, _, _, _, _, _, _, _, _, _),
1472
+
[158] = PINGROUP(158, qdss_cti, gcc_gp, _, _, _, _, _, _, _, _, _),
1473
+
[159] = PINGROUP(159, cci_timer, tsense_clm, _, _, _, _, _, _, _, _, _),
1474
+
[160] = PINGROUP(160, cci_timer, cci_i2c3, _, _, _, _, _, _, _, _, _),
1475
+
[161] = PINGROUP(161, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
1476
+
[162] = PINGROUP(162, qup4_se4_01, qup4_se4_23, _, _, _, _, _, _, _, _, _),
1477
+
[163] = PINGROUP(163, _, _, _, _, _, _, _, _, _, _, egpio),
1478
+
[164] = PINGROUP(164, _, _, _, _, _, _, _, _, _, _, egpio),
1479
+
[165] = PINGROUP(165, _, _, _, _, _, _, _, _, _, _, egpio),
1480
+
[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, egpio),
1481
+
[167] = PINGROUP(167, _, _, _, _, _, _, _, _, _, _, egpio),
1482
+
[168] = PINGROUP(168, _, _, _, _, _, _, _, _, _, _, egpio),
1483
+
[169] = PINGROUP(169, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1484
+
[170] = PINGROUP(170, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1485
+
[171] = PINGROUP(171, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1486
+
[172] = PINGROUP(172, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1487
+
[173] = PINGROUP(173, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1488
+
[174] = PINGROUP(174, _, _, _, _, _, _, _, _, _, _, egpio),
1489
+
[175] = PINGROUP(175, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1490
+
[176] = PINGROUP(176, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1491
+
[177] = PINGROUP(177, _, _, _, _, _, _, _, _, _, _, egpio),
1492
+
[178] = PINGROUP(178, _, _, _, _, _, _, _, _, _, _, egpio),
1493
+
[179] = PINGROUP(179, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1494
+
[180] = PINGROUP(180, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1495
+
[181] = PINGROUP(181, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1496
+
[182] = PINGROUP(182, _, _, _, _, _, _, _, _, _, _, egpio),
1497
+
[183] = PINGROUP(183, _, _, _, _, _, _, _, _, _, _, egpio),
1498
+
[184] = PINGROUP(184, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1499
+
[185] = PINGROUP(185, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1500
+
[186] = PINGROUP(186, _, _, _, _, _, _, _, _, _, _, egpio),
1501
+
[187] = PINGROUP(187, _, _, _, _, _, _, _, _, _, _, egpio),
1502
+
[188] = PINGROUP(188, _, _, _, _, _, _, _, _, _, _, egpio),
1503
+
[189] = PINGROUP(189, _, _, _, _, _, _, _, _, _, _, egpio),
1504
+
[190] = PINGROUP(190, _, _, _, _, _, _, _, _, _, _, egpio),
1505
+
[191] = PINGROUP(191, _, _, _, _, _, _, _, _, _, _, egpio),
1506
+
[192] = PINGROUP(192, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1507
+
[193] = PINGROUP(193, _, _, _, _, _, _, _, _, _, _, egpio),
1508
+
[194] = PINGROUP(194, _, _, _, _, _, _, _, _, _, _, egpio),
1509
+
[195] = PINGROUP(195, _, _, _, _, _, _, _, _, _, _, egpio),
1510
+
[196] = PINGROUP(196, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1511
+
[197] = PINGROUP(197, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1512
+
[198] = PINGROUP(198, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1513
+
[199] = PINGROUP(199, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1514
+
[200] = PINGROUP(200, _, _, _, _, _, _, _, _, _, _, egpio),
1515
+
[201] = PINGROUP(201, _, _, _, _, _, _, _, _, _, _, egpio),
1516
+
[202] = PINGROUP(202, _, _, _, _, _, _, _, _, _, _, egpio),
1517
+
[203] = PINGROUP(203, _, _, _, _, _, _, _, _, _, _, egpio),
1518
+
[204] = PINGROUP(204, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1519
+
[205] = PINGROUP(205, _, _, _, _, _, _, _, _, _, _, egpio),
1520
+
[206] = PINGROUP(206, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1521
+
[207] = PINGROUP(207, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1522
+
[208] = PINGROUP(208, qup2_se4_01, qup2_se4_23, phase_flag, _, _, _, _, _, _, _, egpio),
1523
+
[209] = PINGROUP(209, qup2_se4_01, qup2_se4_23, _, _, _, _, _, _, _, _, egpio),
1524
+
[210] = PINGROUP(210, phase_flag, _, _, _, _, _, _, _, _, _, _),
1525
+
[211] = PINGROUP(211, phase_flag, _, _, _, _, _, _, _, _, _, _),
1526
+
[212] = PINGROUP(212, _, _, _, _, _, _, _, _, _, _, egpio),
1527
+
[213] = PINGROUP(213, _, _, _, _, _, _, _, _, _, _, egpio),
1528
+
[214] = PINGROUP(214, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1529
+
[215] = PINGROUP(215, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1530
+
[216] = PINGROUP(216, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
1531
+
[217] = PINGROUP(217, _, _, _, _, _, _, _, _, _, _, egpio),
1532
+
[218] = PINGROUP(218, _, _, _, _, _, _, _, _, _, _, egpio),
1533
+
[219] = PINGROUP(219, _, _, _, _, _, _, _, _, _, _, _),
1534
+
[220] = PINGROUP(220, _, _, _, _, _, _, _, _, _, _, _),
1535
+
[221] = PINGROUP(221, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),
1536
+
[222] = PINGROUP(222, _, _, _, _, _, _, _, _, _, _, _),
1537
+
[223] = PINGROUP(223, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1538
+
[224] = PINGROUP(224, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1539
+
[225] = PINGROUP(225, tsense_pwm, _, _, _, _, _, _, _, _, _, _),
1540
+
[226] = UFS_RESET(ufs_reset, 0xf1004, 0xf2000),
1541
+
[227] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe6000, 14, 6),
1542
+
[228] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe6000, 11, 3),
1543
+
[229] = SDC_QDSD_PINGROUP(sdc2_data, 0xe6000, 9, 0),
1544
+
};
1545
+
1546
+
static const struct msm_gpio_wakeirq_map hawi_pdc_map[] = {
1547
+
{ 0, 105 }, { 3, 113 }, { 4, 106 }, { 7, 107 }, { 8, 108 }, { 11, 109 },
1548
+
{ 12, 115 }, { 15, 131 }, { 16, 116 }, { 17, 141 }, { 18, 143 }, { 19, 112 },
1549
+
{ 23, 117 }, { 24, 118 }, { 27, 119 }, { 28, 125 }, { 31, 126 }, { 32, 127 },
1550
+
{ 35, 101 }, { 36, 128 }, { 39, 129 }, { 43, 130 }, { 47, 154 }, { 48, 135 },
1551
+
{ 51, 114 }, { 55, 104 }, { 57, 136 }, { 58, 137 }, { 59, 138 }, { 60, 139 },
1552
+
{ 61, 145 }, { 63, 124 }, { 64, 110 }, { 65, 123 }, { 67, 132 }, { 68, 146 },
1553
+
{ 69, 147 }, { 75, 151 }, { 77, 148 }, { 78, 149 }, { 79, 155 }, { 80, 156 },
1554
+
{ 81, 157 }, { 82, 158 }, { 84, 134 }, { 85, 159 }, { 86, 160 }, { 87, 161 },
1555
+
{ 88, 162 }, { 95, 163 }, { 96, 164 }, { 97, 133 }, { 98, 150 }, { 99, 111 },
1556
+
{ 101, 165 }, { 102, 166 }, { 103, 167 }, { 104, 168 }, { 120, 169 }, { 123, 170 },
1557
+
{ 125, 171 }, { 129, 153 }, { 133, 100 }, { 144, 172 }, { 146, 173 }, { 151, 174 },
1558
+
{ 152, 175 }, { 155, 122 }, { 158, 120 }, { 162, 142 }, { 164, 176 }, { 165, 177 },
1559
+
{ 167, 178 }, { 168, 179 }, { 174, 180 }, { 177, 181 }, { 179, 182 }, { 183, 183 },
1560
+
{ 184, 184 }, { 185, 185 }, { 186, 152 }, { 188, 144 }, { 202, 102 }, { 203, 103 },
1561
+
{ 205, 140 }, { 209, 186 }, { 213, 121 }, { 216, 187 }, { 221, 188 }, { 222, 189 },
1562
+
{ 223, 190 }, { 224, 191 }, { 225, 192 },
1563
+
};
1564
+
1565
+
static const struct msm_pinctrl_soc_data hawi_tlmm = {
1566
+
.pins = hawi_pins,
1567
+
.npins = ARRAY_SIZE(hawi_pins),
1568
+
.functions = hawi_functions,
1569
+
.nfunctions = ARRAY_SIZE(hawi_functions),
1570
+
.groups = hawi_groups,
1571
+
.ngroups = ARRAY_SIZE(hawi_groups),
1572
+
.ngpios = 227,
1573
+
.wakeirq_map = hawi_pdc_map,
1574
+
.nwakeirq_map = ARRAY_SIZE(hawi_pdc_map),
1575
+
.egpio_func = 11,
1576
+
};
1577
+
1578
+
static int hawi_tlmm_probe(struct platform_device *pdev)
1579
+
{
1580
+
return msm_pinctrl_probe(pdev, &hawi_tlmm);
1581
+
}
1582
+
1583
+
static const struct of_device_id hawi_tlmm_of_match[] = {
1584
+
{ .compatible = "qcom,hawi-tlmm", },
1585
+
{},
1586
+
};
1587
+
1588
+
static struct platform_driver hawi_tlmm_driver = {
1589
+
.driver = {
1590
+
.name = "hawi-tlmm",
1591
+
.of_match_table = hawi_tlmm_of_match,
1592
+
},
1593
+
.probe = hawi_tlmm_probe,
1594
+
};
1595
+
1596
+
static int __init hawi_tlmm_init(void)
1597
+
{
1598
+
return platform_driver_register(&hawi_tlmm_driver);
1599
+
}
1600
+
arch_initcall(hawi_tlmm_init);
1601
+
1602
+
static void __exit hawi_tlmm_exit(void)
1603
+
{
1604
+
platform_driver_unregister(&hawi_tlmm_driver);
1605
+
}
1606
+
module_exit(hawi_tlmm_exit);
1607
+
1608
+
MODULE_DESCRIPTION("QTI Hawi TLMM driver");
1609
+
MODULE_LICENSE("GPL");
1610
+
MODULE_DEVICE_TABLE(of, hawi_tlmm_of_match);
-1
drivers/pinctrl/qcom/pinctrl-ipq4019.c
-1
drivers/pinctrl/qcom/pinctrl-ipq4019.c
-1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
-1
drivers/pinctrl/qcom/pinctrl-ipq5018.c
+897
drivers/pinctrl/qcom/pinctrl-ipq5210.c
+897
drivers/pinctrl/qcom/pinctrl-ipq5210.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/module.h>
7
+
#include <linux/of.h>
8
+
#include <linux/platform_device.h>
9
+
10
+
#include "pinctrl-msm.h"
11
+
12
+
#define REG_SIZE 0x1000
13
+
#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
14
+
{ \
15
+
.grp = PINCTRL_PINGROUP("gpio" #id, \
16
+
gpio##id##_pins, \
17
+
ARRAY_SIZE(gpio##id##_pins)), \
18
+
.ctl_reg = REG_SIZE * id, \
19
+
.io_reg = 0x4 + REG_SIZE * id, \
20
+
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
21
+
.intr_status_reg = 0xc + REG_SIZE * id, \
22
+
.mux_bit = 2, \
23
+
.pull_bit = 0, \
24
+
.drv_bit = 6, \
25
+
.oe_bit = 9, \
26
+
.in_bit = 0, \
27
+
.out_bit = 1, \
28
+
.intr_enable_bit = 0, \
29
+
.intr_status_bit = 0, \
30
+
.intr_target_bit = 5, \
31
+
.intr_target_kpss_val = 3, \
32
+
.intr_raw_status_bit = 4, \
33
+
.intr_polarity_bit = 1, \
34
+
.intr_detection_bit = 2, \
35
+
.intr_detection_width = 2, \
36
+
.funcs = (int[]){ \
37
+
msm_mux_gpio, /* gpio mode */ \
38
+
msm_mux_##f1, \
39
+
msm_mux_##f2, \
40
+
msm_mux_##f3, \
41
+
msm_mux_##f4, \
42
+
msm_mux_##f5, \
43
+
msm_mux_##f6, \
44
+
msm_mux_##f7, \
45
+
msm_mux_##f8, \
46
+
msm_mux_##f9, \
47
+
}, \
48
+
.nfuncs = 10, \
49
+
}
50
+
51
+
static const struct pinctrl_pin_desc ipq5210_pins[] = {
52
+
PINCTRL_PIN(0, "GPIO_0"),
53
+
PINCTRL_PIN(1, "GPIO_1"),
54
+
PINCTRL_PIN(2, "GPIO_2"),
55
+
PINCTRL_PIN(3, "GPIO_3"),
56
+
PINCTRL_PIN(4, "GPIO_4"),
57
+
PINCTRL_PIN(5, "GPIO_5"),
58
+
PINCTRL_PIN(6, "GPIO_6"),
59
+
PINCTRL_PIN(7, "GPIO_7"),
60
+
PINCTRL_PIN(8, "GPIO_8"),
61
+
PINCTRL_PIN(9, "GPIO_9"),
62
+
PINCTRL_PIN(10, "GPIO_10"),
63
+
PINCTRL_PIN(11, "GPIO_11"),
64
+
PINCTRL_PIN(12, "GPIO_12"),
65
+
PINCTRL_PIN(13, "GPIO_13"),
66
+
PINCTRL_PIN(14, "GPIO_14"),
67
+
PINCTRL_PIN(15, "GPIO_15"),
68
+
PINCTRL_PIN(16, "GPIO_16"),
69
+
PINCTRL_PIN(17, "GPIO_17"),
70
+
PINCTRL_PIN(18, "GPIO_18"),
71
+
PINCTRL_PIN(19, "GPIO_19"),
72
+
PINCTRL_PIN(20, "GPIO_20"),
73
+
PINCTRL_PIN(21, "GPIO_21"),
74
+
PINCTRL_PIN(22, "GPIO_22"),
75
+
PINCTRL_PIN(23, "GPIO_23"),
76
+
PINCTRL_PIN(24, "GPIO_24"),
77
+
PINCTRL_PIN(25, "GPIO_25"),
78
+
PINCTRL_PIN(26, "GPIO_26"),
79
+
PINCTRL_PIN(27, "GPIO_27"),
80
+
PINCTRL_PIN(28, "GPIO_28"),
81
+
PINCTRL_PIN(29, "GPIO_29"),
82
+
PINCTRL_PIN(30, "GPIO_30"),
83
+
PINCTRL_PIN(31, "GPIO_31"),
84
+
PINCTRL_PIN(32, "GPIO_32"),
85
+
PINCTRL_PIN(33, "GPIO_33"),
86
+
PINCTRL_PIN(34, "GPIO_34"),
87
+
PINCTRL_PIN(35, "GPIO_35"),
88
+
PINCTRL_PIN(36, "GPIO_36"),
89
+
PINCTRL_PIN(37, "GPIO_37"),
90
+
PINCTRL_PIN(38, "GPIO_38"),
91
+
PINCTRL_PIN(39, "GPIO_39"),
92
+
PINCTRL_PIN(40, "GPIO_40"),
93
+
PINCTRL_PIN(41, "GPIO_41"),
94
+
PINCTRL_PIN(42, "GPIO_42"),
95
+
PINCTRL_PIN(43, "GPIO_43"),
96
+
PINCTRL_PIN(44, "GPIO_44"),
97
+
PINCTRL_PIN(45, "GPIO_45"),
98
+
PINCTRL_PIN(46, "GPIO_46"),
99
+
PINCTRL_PIN(47, "GPIO_47"),
100
+
PINCTRL_PIN(48, "GPIO_48"),
101
+
PINCTRL_PIN(49, "GPIO_49"),
102
+
PINCTRL_PIN(50, "GPIO_50"),
103
+
PINCTRL_PIN(51, "GPIO_51"),
104
+
PINCTRL_PIN(52, "GPIO_52"),
105
+
PINCTRL_PIN(53, "GPIO_53"),
106
+
};
107
+
108
+
#define DECLARE_MSM_GPIO_PINS(pin) \
109
+
static const unsigned int gpio##pin##_pins[] = { pin }
110
+
DECLARE_MSM_GPIO_PINS(0);
111
+
DECLARE_MSM_GPIO_PINS(1);
112
+
DECLARE_MSM_GPIO_PINS(2);
113
+
DECLARE_MSM_GPIO_PINS(3);
114
+
DECLARE_MSM_GPIO_PINS(4);
115
+
DECLARE_MSM_GPIO_PINS(5);
116
+
DECLARE_MSM_GPIO_PINS(6);
117
+
DECLARE_MSM_GPIO_PINS(7);
118
+
DECLARE_MSM_GPIO_PINS(8);
119
+
DECLARE_MSM_GPIO_PINS(9);
120
+
DECLARE_MSM_GPIO_PINS(10);
121
+
DECLARE_MSM_GPIO_PINS(11);
122
+
DECLARE_MSM_GPIO_PINS(12);
123
+
DECLARE_MSM_GPIO_PINS(13);
124
+
DECLARE_MSM_GPIO_PINS(14);
125
+
DECLARE_MSM_GPIO_PINS(15);
126
+
DECLARE_MSM_GPIO_PINS(16);
127
+
DECLARE_MSM_GPIO_PINS(17);
128
+
DECLARE_MSM_GPIO_PINS(18);
129
+
DECLARE_MSM_GPIO_PINS(19);
130
+
DECLARE_MSM_GPIO_PINS(20);
131
+
DECLARE_MSM_GPIO_PINS(21);
132
+
DECLARE_MSM_GPIO_PINS(22);
133
+
DECLARE_MSM_GPIO_PINS(23);
134
+
DECLARE_MSM_GPIO_PINS(24);
135
+
DECLARE_MSM_GPIO_PINS(25);
136
+
DECLARE_MSM_GPIO_PINS(26);
137
+
DECLARE_MSM_GPIO_PINS(27);
138
+
DECLARE_MSM_GPIO_PINS(28);
139
+
DECLARE_MSM_GPIO_PINS(29);
140
+
DECLARE_MSM_GPIO_PINS(30);
141
+
DECLARE_MSM_GPIO_PINS(31);
142
+
DECLARE_MSM_GPIO_PINS(32);
143
+
DECLARE_MSM_GPIO_PINS(33);
144
+
DECLARE_MSM_GPIO_PINS(34);
145
+
DECLARE_MSM_GPIO_PINS(35);
146
+
DECLARE_MSM_GPIO_PINS(36);
147
+
DECLARE_MSM_GPIO_PINS(37);
148
+
DECLARE_MSM_GPIO_PINS(38);
149
+
DECLARE_MSM_GPIO_PINS(39);
150
+
DECLARE_MSM_GPIO_PINS(40);
151
+
DECLARE_MSM_GPIO_PINS(41);
152
+
DECLARE_MSM_GPIO_PINS(42);
153
+
DECLARE_MSM_GPIO_PINS(43);
154
+
DECLARE_MSM_GPIO_PINS(44);
155
+
DECLARE_MSM_GPIO_PINS(45);
156
+
DECLARE_MSM_GPIO_PINS(46);
157
+
DECLARE_MSM_GPIO_PINS(47);
158
+
DECLARE_MSM_GPIO_PINS(48);
159
+
DECLARE_MSM_GPIO_PINS(49);
160
+
DECLARE_MSM_GPIO_PINS(50);
161
+
DECLARE_MSM_GPIO_PINS(51);
162
+
DECLARE_MSM_GPIO_PINS(52);
163
+
DECLARE_MSM_GPIO_PINS(53);
164
+
165
+
enum ipq5210_functions {
166
+
msm_mux_atest_char_start,
167
+
msm_mux_atest_char_status0,
168
+
msm_mux_atest_char_status1,
169
+
msm_mux_atest_char_status2,
170
+
msm_mux_atest_char_status3,
171
+
msm_mux_atest_tic_en,
172
+
msm_mux_audio_pri,
173
+
msm_mux_audio_pri_mclk_out0,
174
+
msm_mux_audio_pri_mclk_in0,
175
+
msm_mux_audio_pri_mclk_out1,
176
+
msm_mux_audio_pri_mclk_in1,
177
+
msm_mux_audio_pri_mclk_out2,
178
+
msm_mux_audio_pri_mclk_in2,
179
+
msm_mux_audio_pri_mclk_out3,
180
+
msm_mux_audio_pri_mclk_in3,
181
+
msm_mux_audio_sec,
182
+
msm_mux_audio_sec_mclk_out0,
183
+
msm_mux_audio_sec_mclk_in0,
184
+
msm_mux_audio_sec_mclk_out1,
185
+
msm_mux_audio_sec_mclk_in1,
186
+
msm_mux_audio_sec_mclk_out2,
187
+
msm_mux_audio_sec_mclk_in2,
188
+
msm_mux_audio_sec_mclk_out3,
189
+
msm_mux_audio_sec_mclk_in3,
190
+
msm_mux_core_voltage_0,
191
+
msm_mux_cri_trng0,
192
+
msm_mux_cri_trng1,
193
+
msm_mux_cri_trng2,
194
+
msm_mux_cri_trng3,
195
+
msm_mux_dbg_out_clk,
196
+
msm_mux_dg_out,
197
+
msm_mux_gcc_plltest_bypassnl,
198
+
msm_mux_gcc_plltest_resetn,
199
+
msm_mux_gcc_tlmm,
200
+
msm_mux_gpio,
201
+
msm_mux_led0,
202
+
msm_mux_led1,
203
+
msm_mux_led2,
204
+
msm_mux_mdc_mst,
205
+
msm_mux_mdc_slv0,
206
+
msm_mux_mdc_slv1,
207
+
msm_mux_mdc_slv2,
208
+
msm_mux_mdio_mst,
209
+
msm_mux_mdio_slv0,
210
+
msm_mux_mdio_slv1,
211
+
msm_mux_mdio_slv2,
212
+
msm_mux_mux_tod_out,
213
+
msm_mux_pcie0_clk_req_n,
214
+
msm_mux_pcie0_wake,
215
+
msm_mux_pcie1_clk_req_n,
216
+
msm_mux_pcie1_wake,
217
+
msm_mux_pll_test,
218
+
msm_mux_pon_active_led,
219
+
msm_mux_pon_mux_sel,
220
+
msm_mux_pon_rx,
221
+
msm_mux_pon_rx_los,
222
+
msm_mux_pon_tx,
223
+
msm_mux_pon_tx_burst,
224
+
msm_mux_pon_tx_dis,
225
+
msm_mux_pon_tx_fault,
226
+
msm_mux_pon_tx_sd,
227
+
msm_mux_gpn_rx_los,
228
+
msm_mux_gpn_tx_burst,
229
+
msm_mux_gpn_tx_dis,
230
+
msm_mux_gpn_tx_fault,
231
+
msm_mux_gpn_tx_sd,
232
+
msm_mux_pps,
233
+
msm_mux_pwm0,
234
+
msm_mux_pwm1,
235
+
msm_mux_pwm2,
236
+
msm_mux_pwm3,
237
+
msm_mux_qdss_cti_trig_in_a0,
238
+
msm_mux_qdss_cti_trig_in_a1,
239
+
msm_mux_qdss_cti_trig_in_b0,
240
+
msm_mux_qdss_cti_trig_in_b1,
241
+
msm_mux_qdss_cti_trig_out_a0,
242
+
msm_mux_qdss_cti_trig_out_a1,
243
+
msm_mux_qdss_cti_trig_out_b0,
244
+
msm_mux_qdss_cti_trig_out_b1,
245
+
msm_mux_qdss_traceclk_a,
246
+
msm_mux_qdss_tracectl_a,
247
+
msm_mux_qdss_tracedata_a,
248
+
msm_mux_qrng_rosc0,
249
+
msm_mux_qrng_rosc1,
250
+
msm_mux_qrng_rosc2,
251
+
msm_mux_qspi_data,
252
+
msm_mux_qspi_clk,
253
+
msm_mux_qspi_cs_n,
254
+
msm_mux_qup_se0,
255
+
msm_mux_qup_se1,
256
+
msm_mux_qup_se2,
257
+
msm_mux_qup_se3,
258
+
msm_mux_qup_se4,
259
+
msm_mux_qup_se5,
260
+
msm_mux_qup_se5_l1,
261
+
msm_mux_resout,
262
+
msm_mux_rx_los0,
263
+
msm_mux_rx_los1,
264
+
msm_mux_rx_los2,
265
+
msm_mux_sdc_clk,
266
+
msm_mux_sdc_cmd,
267
+
msm_mux_sdc_data,
268
+
msm_mux_tsens_max,
269
+
msm_mux__,
270
+
};
271
+
272
+
static const char *const gpio_groups[] = {
273
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
274
+
"gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13",
275
+
"gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20",
276
+
"gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
277
+
"gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34",
278
+
"gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41",
279
+
"gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
280
+
"gpio49", "gpio50", "gpio51", "gpio52", "gpio53",
281
+
};
282
+
283
+
static const char *const atest_char_start_groups[] = {
284
+
"gpio46",
285
+
};
286
+
287
+
static const char *const atest_char_status0_groups[] = {
288
+
"gpio34",
289
+
};
290
+
291
+
static const char *const atest_char_status1_groups[] = {
292
+
"gpio35",
293
+
};
294
+
295
+
static const char *const atest_char_status2_groups[] = {
296
+
"gpio36",
297
+
};
298
+
299
+
static const char *const atest_char_status3_groups[] = {
300
+
"gpio37",
301
+
};
302
+
303
+
static const char *const atest_tic_en_groups[] = {
304
+
"gpio42",
305
+
};
306
+
307
+
static const char *const audio_pri_groups[] = {
308
+
"gpio34", "gpio35", "gpio36", "gpio37",
309
+
};
310
+
311
+
static const char *const audio_pri_mclk_out0_groups[] = {
312
+
"gpio12",
313
+
};
314
+
315
+
static const char *const audio_pri_mclk_in0_groups[] = {
316
+
"gpio12",
317
+
};
318
+
319
+
static const char *const audio_pri_mclk_out1_groups[] = {
320
+
"gpio19",
321
+
};
322
+
323
+
static const char *const audio_pri_mclk_in1_groups[] = {
324
+
"gpio19",
325
+
};
326
+
327
+
static const char *const audio_pri_mclk_out2_groups[] = {
328
+
"gpio8",
329
+
};
330
+
331
+
static const char *const audio_pri_mclk_in2_groups[] = {
332
+
"gpio8",
333
+
};
334
+
335
+
static const char *const audio_pri_mclk_out3_groups[] = {
336
+
"gpio13",
337
+
};
338
+
339
+
static const char *const audio_pri_mclk_in3_groups[] = {
340
+
"gpio13",
341
+
};
342
+
343
+
static const char *const audio_sec_mclk_out0_groups[] = {
344
+
"gpio17",
345
+
};
346
+
347
+
static const char *const audio_sec_mclk_in0_groups[] = {
348
+
"gpio17",
349
+
};
350
+
351
+
static const char *const audio_sec_mclk_out1_groups[] = {
352
+
"gpio16",
353
+
};
354
+
355
+
static const char *const audio_sec_mclk_in1_groups[] = {
356
+
"gpio16",
357
+
};
358
+
359
+
static const char *const audio_sec_mclk_out2_groups[] = {
360
+
"gpio49",
361
+
};
362
+
363
+
static const char *const audio_sec_mclk_in2_groups[] = {
364
+
"gpio49",
365
+
};
366
+
367
+
static const char *const audio_sec_mclk_out3_groups[] = {
368
+
"gpio50",
369
+
};
370
+
371
+
static const char *const audio_sec_mclk_in3_groups[] = {
372
+
"gpio50",
373
+
};
374
+
375
+
static const char *const audio_sec_groups[] = {
376
+
"gpio40", "gpio41", "gpio42", "gpio43",
377
+
};
378
+
379
+
static const char *const core_voltage_0_groups[] = {
380
+
"gpio22",
381
+
};
382
+
383
+
static const char *const cri_trng0_groups[] = {
384
+
"gpio6",
385
+
};
386
+
387
+
static const char *const cri_trng1_groups[] = {
388
+
"gpio7",
389
+
};
390
+
391
+
static const char *const cri_trng2_groups[] = {
392
+
"gpio8",
393
+
};
394
+
395
+
static const char *const cri_trng3_groups[] = {
396
+
"gpio9",
397
+
};
398
+
399
+
static const char *const dbg_out_clk_groups[] = {
400
+
"gpio23",
401
+
};
402
+
403
+
static const char *const dg_out_groups[] = {
404
+
"gpio46",
405
+
};
406
+
407
+
static const char *const gcc_plltest_bypassnl_groups[] = {
408
+
"gpio38",
409
+
};
410
+
411
+
static const char *const gcc_plltest_resetn_groups[] = {
412
+
"gpio40",
413
+
};
414
+
415
+
static const char *const gcc_tlmm_groups[] = {
416
+
"gpio39",
417
+
};
418
+
419
+
static const char *const led0_groups[] = {
420
+
"gpio6", "gpio23", "gpio39",
421
+
};
422
+
423
+
static const char *const led1_groups[] = {
424
+
"gpio7", "gpio27", "gpio39",
425
+
};
426
+
427
+
static const char *const led2_groups[] = {
428
+
"gpio9", "gpio26", "gpio38",
429
+
};
430
+
431
+
static const char *const mdc_mst_groups[] = {
432
+
"gpio26",
433
+
};
434
+
435
+
static const char *const mdc_slv0_groups[] = {
436
+
"gpio31",
437
+
};
438
+
439
+
static const char *const mdc_slv1_groups[] = {
440
+
"gpio20",
441
+
};
442
+
443
+
static const char *const mdc_slv2_groups[] = {
444
+
"gpio47",
445
+
};
446
+
447
+
static const char *const mdio_mst_groups[] = {
448
+
"gpio27",
449
+
};
450
+
451
+
static const char *const mdio_slv0_groups[] = {
452
+
"gpio33",
453
+
};
454
+
455
+
static const char *const mdio_slv1_groups[] = {
456
+
"gpio21",
457
+
};
458
+
459
+
static const char *const mdio_slv2_groups[] = {
460
+
"gpio49",
461
+
};
462
+
463
+
static const char *const mux_tod_out_groups[] = {
464
+
"gpio19",
465
+
};
466
+
467
+
static const char *const pcie0_clk_req_n_groups[] = {
468
+
"gpio31",
469
+
};
470
+
471
+
static const char *const pcie0_wake_groups[] = {
472
+
"gpio33",
473
+
};
474
+
475
+
static const char *const pcie1_clk_req_n_groups[] = {
476
+
"gpio28",
477
+
};
478
+
479
+
static const char *const pcie1_wake_groups[] = {
480
+
"gpio30",
481
+
};
482
+
483
+
static const char *const pll_test_groups[] = {
484
+
"gpio18",
485
+
};
486
+
487
+
static const char *const pon_active_led_groups[] = {
488
+
"gpio11",
489
+
};
490
+
491
+
static const char *const pon_mux_sel_groups[] = {
492
+
"gpio45",
493
+
};
494
+
495
+
static const char *const pon_rx_groups[] = {
496
+
"gpio48",
497
+
};
498
+
499
+
static const char *const pon_rx_los_groups[] = {
500
+
"gpio10",
501
+
};
502
+
503
+
static const char *const pon_tx_groups[] = {
504
+
"gpio15",
505
+
};
506
+
507
+
static const char *const pon_tx_burst_groups[] = {
508
+
"gpio14",
509
+
};
510
+
511
+
static const char *const pon_tx_dis_groups[] = {
512
+
"gpio12",
513
+
};
514
+
515
+
static const char *const pon_tx_fault_groups[] = {
516
+
"gpio17",
517
+
};
518
+
519
+
static const char *const pon_tx_sd_groups[] = {
520
+
"gpio16",
521
+
};
522
+
523
+
static const char *const gpn_rx_los_groups[] = {
524
+
"gpio47",
525
+
};
526
+
527
+
static const char *const gpn_tx_burst_groups[] = {
528
+
"gpio51",
529
+
};
530
+
531
+
static const char *const gpn_tx_dis_groups[] = {
532
+
"gpio13",
533
+
};
534
+
535
+
static const char *const gpn_tx_fault_groups[] = {
536
+
"gpio49",
537
+
};
538
+
539
+
static const char *const gpn_tx_sd_groups[] = {
540
+
"gpio50",
541
+
};
542
+
543
+
static const char *const pps_groups[] = {
544
+
"gpio18",
545
+
};
546
+
547
+
static const char *const pwm0_groups[] = {
548
+
"gpio10", "gpio11", "gpio12", "gpio13",
549
+
};
550
+
551
+
static const char *const pwm1_groups[] = {
552
+
"gpio6", "gpio7", "gpio8", "gpio9",
553
+
};
554
+
555
+
static const char *const pwm2_groups[] = {
556
+
"gpio0", "gpio1", "gpio2", "gpio3",
557
+
};
558
+
559
+
static const char *const pwm3_groups[] = {
560
+
"gpio22",
561
+
};
562
+
563
+
static const char *const qdss_cti_trig_in_a0_groups[] = {
564
+
"gpio30",
565
+
};
566
+
567
+
static const char *const qdss_cti_trig_in_a1_groups[] = {
568
+
"gpio33",
569
+
};
570
+
571
+
static const char *const qdss_cti_trig_in_b0_groups[] = {
572
+
"gpio34",
573
+
};
574
+
575
+
static const char *const qdss_cti_trig_in_b1_groups[] = {
576
+
"gpio37",
577
+
};
578
+
579
+
static const char *const qdss_cti_trig_out_a0_groups[] = {
580
+
"gpio28",
581
+
};
582
+
583
+
static const char *const qdss_cti_trig_out_a1_groups[] = {
584
+
"gpio31",
585
+
};
586
+
587
+
static const char *const qdss_cti_trig_out_b0_groups[] = {
588
+
"gpio16",
589
+
};
590
+
591
+
static const char *const qdss_cti_trig_out_b1_groups[] = {
592
+
"gpio35",
593
+
};
594
+
595
+
static const char *const qdss_traceclk_a_groups[] = {
596
+
"gpio23",
597
+
};
598
+
599
+
static const char *const qdss_tracectl_a_groups[] = {
600
+
"gpio26",
601
+
};
602
+
603
+
static const char *const qdss_tracedata_a_groups[] = {
604
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
605
+
"gpio12", "gpio13", "gpio14", "gpio15", "gpio20", "gpio21",
606
+
"gpio38", "gpio39", "gpio40", "gpio41",
607
+
};
608
+
609
+
static const char *const qrng_rosc0_groups[] = {
610
+
"gpio12",
611
+
};
612
+
613
+
static const char *const qrng_rosc1_groups[] = {
614
+
"gpio13",
615
+
};
616
+
617
+
static const char *const qrng_rosc2_groups[] = {
618
+
"gpio14",
619
+
};
620
+
621
+
static const char *const qspi_data_groups[] = {
622
+
"gpio0", "gpio1", "gpio2", "gpio3",
623
+
};
624
+
625
+
static const char *const qspi_clk_groups[] = {
626
+
"gpio5",
627
+
};
628
+
629
+
static const char *const qspi_cs_n_groups[] = {
630
+
"gpio4",
631
+
};
632
+
633
+
static const char *const qup_se0_groups[] = {
634
+
"gpio6", "gpio7", "gpio8", "gpio9", "gpio14", "gpio15",
635
+
};
636
+
637
+
static const char *const qup_se1_groups[] = {
638
+
"gpio28", "gpio30", "gpio38", "gpio39",
639
+
};
640
+
641
+
static const char *const qup_se2_groups[] = {
642
+
"gpio12", "gpio13", "gpio20", "gpio21", "gpio52", "gpio53",
643
+
};
644
+
645
+
static const char *const qup_se3_groups[] = {
646
+
"gpio10", "gpio11", "gpio22", "gpio23",
647
+
};
648
+
649
+
static const char *const qup_se4_groups[] = {
650
+
"gpio40", "gpio41", "gpio42", "gpio43", "gpio52", "gpio53",
651
+
};
652
+
653
+
static const char *const qup_se5_groups[] = {
654
+
"gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52",
655
+
};
656
+
657
+
static const char *const qup_se5_l1_groups[] = {
658
+
"gpio52", "gpio53",
659
+
};
660
+
661
+
static const char *const resout_groups[] = {
662
+
"gpio44",
663
+
};
664
+
665
+
static const char *const rx_los0_groups[] = {
666
+
"gpio37", "gpio42",
667
+
};
668
+
669
+
static const char *const rx_los1_groups[] = {
670
+
"gpio36", "gpio41",
671
+
};
672
+
673
+
static const char *const rx_los2_groups[] = {
674
+
"gpio35", "gpio40",
675
+
};
676
+
677
+
static const char *const sdc_clk_groups[] = {
678
+
"gpio5",
679
+
};
680
+
681
+
static const char *const sdc_cmd_groups[] = {
682
+
"gpio4",
683
+
};
684
+
685
+
static const char *const sdc_data_groups[] = {
686
+
"gpio0", "gpio1", "gpio2", "gpio3",
687
+
};
688
+
689
+
static const char *const tsens_max_groups[] = {
690
+
"gpio20",
691
+
};
692
+
693
+
static const struct pinfunction ipq5210_functions[] = {
694
+
MSM_PIN_FUNCTION(atest_char_start),
695
+
MSM_PIN_FUNCTION(atest_char_status0),
696
+
MSM_PIN_FUNCTION(atest_char_status1),
697
+
MSM_PIN_FUNCTION(atest_char_status2),
698
+
MSM_PIN_FUNCTION(atest_char_status3),
699
+
MSM_PIN_FUNCTION(atest_tic_en),
700
+
MSM_PIN_FUNCTION(audio_pri),
701
+
MSM_PIN_FUNCTION(audio_pri_mclk_out0),
702
+
MSM_PIN_FUNCTION(audio_pri_mclk_in0),
703
+
MSM_PIN_FUNCTION(audio_pri_mclk_out1),
704
+
MSM_PIN_FUNCTION(audio_pri_mclk_in1),
705
+
MSM_PIN_FUNCTION(audio_pri_mclk_out2),
706
+
MSM_PIN_FUNCTION(audio_pri_mclk_in2),
707
+
MSM_PIN_FUNCTION(audio_pri_mclk_out3),
708
+
MSM_PIN_FUNCTION(audio_pri_mclk_in3),
709
+
MSM_PIN_FUNCTION(audio_sec),
710
+
MSM_PIN_FUNCTION(audio_sec_mclk_out0),
711
+
MSM_PIN_FUNCTION(audio_sec_mclk_in0),
712
+
MSM_PIN_FUNCTION(audio_sec_mclk_out1),
713
+
MSM_PIN_FUNCTION(audio_sec_mclk_in1),
714
+
MSM_PIN_FUNCTION(audio_sec_mclk_out2),
715
+
MSM_PIN_FUNCTION(audio_sec_mclk_in2),
716
+
MSM_PIN_FUNCTION(audio_sec_mclk_out3),
717
+
MSM_PIN_FUNCTION(audio_sec_mclk_in3),
718
+
MSM_PIN_FUNCTION(core_voltage_0),
719
+
MSM_PIN_FUNCTION(cri_trng0),
720
+
MSM_PIN_FUNCTION(cri_trng1),
721
+
MSM_PIN_FUNCTION(cri_trng2),
722
+
MSM_PIN_FUNCTION(cri_trng3),
723
+
MSM_PIN_FUNCTION(dbg_out_clk),
724
+
MSM_PIN_FUNCTION(dg_out),
725
+
MSM_PIN_FUNCTION(gcc_plltest_bypassnl),
726
+
MSM_PIN_FUNCTION(gcc_plltest_resetn),
727
+
MSM_PIN_FUNCTION(gcc_tlmm),
728
+
MSM_GPIO_PIN_FUNCTION(gpio),
729
+
MSM_PIN_FUNCTION(led0),
730
+
MSM_PIN_FUNCTION(led1),
731
+
MSM_PIN_FUNCTION(led2),
732
+
MSM_PIN_FUNCTION(mdc_mst),
733
+
MSM_PIN_FUNCTION(mdc_slv0),
734
+
MSM_PIN_FUNCTION(mdc_slv1),
735
+
MSM_PIN_FUNCTION(mdc_slv2),
736
+
MSM_PIN_FUNCTION(mdio_mst),
737
+
MSM_PIN_FUNCTION(mdio_slv0),
738
+
MSM_PIN_FUNCTION(mdio_slv1),
739
+
MSM_PIN_FUNCTION(mdio_slv2),
740
+
MSM_PIN_FUNCTION(mux_tod_out),
741
+
MSM_PIN_FUNCTION(pcie0_clk_req_n),
742
+
MSM_PIN_FUNCTION(pcie0_wake),
743
+
MSM_PIN_FUNCTION(pcie1_clk_req_n),
744
+
MSM_PIN_FUNCTION(pcie1_wake),
745
+
MSM_PIN_FUNCTION(pll_test),
746
+
MSM_PIN_FUNCTION(pon_active_led),
747
+
MSM_PIN_FUNCTION(pon_mux_sel),
748
+
MSM_PIN_FUNCTION(pon_rx),
749
+
MSM_PIN_FUNCTION(pon_rx_los),
750
+
MSM_PIN_FUNCTION(pon_tx),
751
+
MSM_PIN_FUNCTION(pon_tx_burst),
752
+
MSM_PIN_FUNCTION(pon_tx_dis),
753
+
MSM_PIN_FUNCTION(pon_tx_fault),
754
+
MSM_PIN_FUNCTION(pon_tx_sd),
755
+
MSM_PIN_FUNCTION(gpn_rx_los),
756
+
MSM_PIN_FUNCTION(gpn_tx_burst),
757
+
MSM_PIN_FUNCTION(gpn_tx_dis),
758
+
MSM_PIN_FUNCTION(gpn_tx_fault),
759
+
MSM_PIN_FUNCTION(gpn_tx_sd),
760
+
MSM_PIN_FUNCTION(pps),
761
+
MSM_PIN_FUNCTION(pwm0),
762
+
MSM_PIN_FUNCTION(pwm1),
763
+
MSM_PIN_FUNCTION(pwm2),
764
+
MSM_PIN_FUNCTION(pwm3),
765
+
MSM_PIN_FUNCTION(qdss_cti_trig_in_a0),
766
+
MSM_PIN_FUNCTION(qdss_cti_trig_in_a1),
767
+
MSM_PIN_FUNCTION(qdss_cti_trig_in_b0),
768
+
MSM_PIN_FUNCTION(qdss_cti_trig_in_b1),
769
+
MSM_PIN_FUNCTION(qdss_cti_trig_out_a0),
770
+
MSM_PIN_FUNCTION(qdss_cti_trig_out_a1),
771
+
MSM_PIN_FUNCTION(qdss_cti_trig_out_b0),
772
+
MSM_PIN_FUNCTION(qdss_cti_trig_out_b1),
773
+
MSM_PIN_FUNCTION(qdss_traceclk_a),
774
+
MSM_PIN_FUNCTION(qdss_tracectl_a),
775
+
MSM_PIN_FUNCTION(qdss_tracedata_a),
776
+
MSM_PIN_FUNCTION(qrng_rosc0),
777
+
MSM_PIN_FUNCTION(qrng_rosc1),
778
+
MSM_PIN_FUNCTION(qrng_rosc2),
779
+
MSM_PIN_FUNCTION(qspi_data),
780
+
MSM_PIN_FUNCTION(qspi_clk),
781
+
MSM_PIN_FUNCTION(qspi_cs_n),
782
+
MSM_PIN_FUNCTION(qup_se0),
783
+
MSM_PIN_FUNCTION(qup_se1),
784
+
MSM_PIN_FUNCTION(qup_se2),
785
+
MSM_PIN_FUNCTION(qup_se3),
786
+
MSM_PIN_FUNCTION(qup_se4),
787
+
MSM_PIN_FUNCTION(qup_se5),
788
+
MSM_PIN_FUNCTION(qup_se5_l1),
789
+
MSM_PIN_FUNCTION(resout),
790
+
MSM_PIN_FUNCTION(rx_los0),
791
+
MSM_PIN_FUNCTION(rx_los1),
792
+
MSM_PIN_FUNCTION(rx_los2),
793
+
MSM_PIN_FUNCTION(sdc_clk),
794
+
MSM_PIN_FUNCTION(sdc_cmd),
795
+
MSM_PIN_FUNCTION(sdc_data),
796
+
MSM_PIN_FUNCTION(tsens_max),
797
+
};
798
+
799
+
static const struct msm_pingroup ipq5210_groups[] = {
800
+
[0] = PINGROUP(0, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
801
+
[1] = PINGROUP(1, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
802
+
[2] = PINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
803
+
[3] = PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
804
+
[4] = PINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),
805
+
[5] = PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
806
+
[6] = PINGROUP(6, qup_se0, led0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _),
807
+
[7] = PINGROUP(7, qup_se0, led1, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _),
808
+
[8] = PINGROUP(8, qup_se0, pwm1, audio_pri_mclk_out2, audio_pri_mclk_in2, _, cri_trng2, qdss_tracedata_a, _, _),
809
+
[9] = PINGROUP(9, qup_se0, led2, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _),
810
+
[10] = PINGROUP(10, pon_rx_los, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),
811
+
[11] = PINGROUP(11, pon_active_led, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),
812
+
[12] = PINGROUP(12, pon_tx_dis, qup_se2, pwm0, audio_pri_mclk_out0, audio_pri_mclk_in0, _, qrng_rosc0, qdss_tracedata_a, _),
813
+
[13] = PINGROUP(13, gpn_tx_dis, qup_se2, pwm0, audio_pri_mclk_out3, audio_pri_mclk_in3, _, qrng_rosc1, qdss_tracedata_a, _),
814
+
[14] = PINGROUP(14, pon_tx_burst, qup_se0, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _),
815
+
[15] = PINGROUP(15, pon_tx, qup_se0, _, qdss_tracedata_a, _, _, _, _, _),
816
+
[16] = PINGROUP(16, pon_tx_sd, audio_sec_mclk_out1, audio_sec_mclk_in1, qdss_cti_trig_out_b0, _, _, _, _, _),
817
+
[17] = PINGROUP(17, pon_tx_fault, audio_sec_mclk_out0, audio_sec_mclk_in0, _, _, _, _, _, _),
818
+
[18] = PINGROUP(18, pps, pll_test, _, _, _, _, _, _, _),
819
+
[19] = PINGROUP(19, mux_tod_out, audio_pri_mclk_out1, audio_pri_mclk_in1, _, _, _, _, _, _),
820
+
[20] = PINGROUP(20, qup_se2, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _),
821
+
[21] = PINGROUP(21, qup_se2, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _),
822
+
[22] = PINGROUP(22, core_voltage_0, qup_se3, pwm3, _, _, _, _, _, _),
823
+
[23] = PINGROUP(23, led0, qup_se3, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _),
824
+
[24] = PINGROUP(24, _, _, _, _, _, _, _, _, _),
825
+
[25] = PINGROUP(25, _, _, _, _, _, _, _, _, _),
826
+
[26] = PINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _),
827
+
[27] = PINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _),
828
+
[28] = PINGROUP(28, pcie1_clk_req_n, qup_se1, _, _, qdss_cti_trig_out_a0, _, _, _, _),
829
+
[29] = PINGROUP(29, _, _, _, _, _, _, _, _, _),
830
+
[30] = PINGROUP(30, pcie1_wake, qup_se1, _, _, qdss_cti_trig_in_a0, _, _, _, _),
831
+
[31] = PINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _),
832
+
[32] = PINGROUP(32, _, _, _, _, _, _, _, _, _),
833
+
[33] = PINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _),
834
+
[34] = PINGROUP(34, audio_pri, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _),
835
+
[35] = PINGROUP(35, audio_pri, rx_los2, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _),
836
+
[36] = PINGROUP(36, audio_pri, _, rx_los1, atest_char_status2, _, _, _, _, _),
837
+
[37] = PINGROUP(37, audio_pri, rx_los0, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _),
838
+
[38] = PINGROUP(38, qup_se1, led2, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _),
839
+
[39] = PINGROUP(39, qup_se1, led1, led0, gcc_tlmm, qdss_tracedata_a, _, _, _, _),
840
+
[40] = PINGROUP(40, qup_se4, rx_los2, audio_sec, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _),
841
+
[41] = PINGROUP(41, qup_se4, rx_los1, audio_sec, qdss_tracedata_a, _, _, _, _, _),
842
+
[42] = PINGROUP(42, qup_se4, rx_los0, audio_sec, atest_tic_en, _, _, _, _, _),
843
+
[43] = PINGROUP(43, qup_se4, audio_sec, _, _, _, _, _, _, _),
844
+
[44] = PINGROUP(44, resout, _, _, _, _, _, _, _, _),
845
+
[45] = PINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _),
846
+
[46] = PINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _),
847
+
[47] = PINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5, _, _, _, _, _, _),
848
+
[48] = PINGROUP(48, pon_rx, qup_se5, _, _, _, _, _, _, _),
849
+
[49] = PINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5, audio_sec_mclk_out2, audio_sec_mclk_in2, _, _, _, _),
850
+
[50] = PINGROUP(50, gpn_tx_sd, qup_se5, audio_sec_mclk_out3, audio_sec_mclk_in3, _, _, _, _, _),
851
+
[51] = PINGROUP(51, gpn_tx_burst, qup_se5, _, _, _, _, _, _, _),
852
+
[52] = PINGROUP(52, qup_se2, qup_se5, qup_se4, qup_se5_l1, _, _, _, _, _),
853
+
[53] = PINGROUP(53, qup_se2, qup_se4, qup_se5_l1, _, _, _, _, _, _),
854
+
};
855
+
856
+
static const struct msm_pinctrl_soc_data ipq5210_tlmm = {
857
+
.pins = ipq5210_pins,
858
+
.npins = ARRAY_SIZE(ipq5210_pins),
859
+
.functions = ipq5210_functions,
860
+
.nfunctions = ARRAY_SIZE(ipq5210_functions),
861
+
.groups = ipq5210_groups,
862
+
.ngroups = ARRAY_SIZE(ipq5210_groups),
863
+
.ngpios = 54,
864
+
};
865
+
866
+
static const struct of_device_id ipq5210_tlmm_of_match[] = {
867
+
{ .compatible = "qcom,ipq5210-tlmm", },
868
+
{ },
869
+
};
870
+
871
+
static int ipq5210_tlmm_probe(struct platform_device *pdev)
872
+
{
873
+
return msm_pinctrl_probe(pdev, &ipq5210_tlmm);
874
+
}
875
+
876
+
static struct platform_driver ipq5210_tlmm_driver = {
877
+
.driver = {
878
+
.name = "ipq5210-tlmm",
879
+
.of_match_table = ipq5210_tlmm_of_match,
880
+
},
881
+
.probe = ipq5210_tlmm_probe,
882
+
};
883
+
884
+
static int __init ipq5210_tlmm_init(void)
885
+
{
886
+
return platform_driver_register(&ipq5210_tlmm_driver);
887
+
}
888
+
arch_initcall(ipq5210_tlmm_init);
889
+
890
+
static void __exit ipq5210_tlmm_exit(void)
891
+
{
892
+
platform_driver_unregister(&ipq5210_tlmm_driver);
893
+
}
894
+
module_exit(ipq5210_tlmm_exit);
895
+
896
+
MODULE_DESCRIPTION("QTI IPQ5210 TLMM driver");
897
+
MODULE_LICENSE("GPL");
-1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
-1
drivers/pinctrl/qcom/pinctrl-ipq5332.c
-1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
-1
drivers/pinctrl/qcom/pinctrl-ipq5424.c
-1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
-1
drivers/pinctrl/qcom/pinctrl-ipq6018.c
-1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
-1
drivers/pinctrl/qcom/pinctrl-ipq8074.c
-1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
-1
drivers/pinctrl/qcom/pinctrl-ipq9574.c
-3
drivers/pinctrl/qcom/pinctrl-kaanapali.c
-3
drivers/pinctrl/qcom/pinctrl-kaanapali.c
···
34
34
.io_reg = 0x4 + REG_SIZE * id, \
35
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
36
.intr_status_reg = 0xc + REG_SIZE * id, \
37
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
63
64
.io_reg = 0, \
64
65
.intr_cfg_reg = 0, \
65
66
.intr_status_reg = 0, \
66
-
.intr_target_reg = 0, \
67
67
.mux_bit = -1, \
68
68
.pull_bit = pull, \
69
69
.drv_bit = drv, \
···
87
89
.io_reg = io, \
88
90
.intr_cfg_reg = 0, \
89
91
.intr_status_reg = 0, \
90
-
.intr_target_reg = 0, \
91
92
.mux_bit = -1, \
92
93
.pull_bit = 3, \
93
94
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-mdm9607.c
-2
drivers/pinctrl/qcom/pinctrl-mdm9607.c
···
225
225
.io_reg = 0x4 + 0x1000 * id, \
226
226
.intr_cfg_reg = 0x8 + 0x1000 * id, \
227
227
.intr_status_reg = 0xc + 0x1000 * id, \
228
-
.intr_target_reg = 0x8 + 0x1000 * id, \
229
228
.mux_bit = 2, \
230
229
.pull_bit = 0, \
231
230
.drv_bit = 6, \
···
250
251
.io_reg = 0, \
251
252
.intr_cfg_reg = 0, \
252
253
.intr_status_reg = 0, \
253
-
.intr_target_reg = 0, \
254
254
.mux_bit = -1, \
255
255
.pull_bit = pull, \
256
256
.drv_bit = drv, \
+217
drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
+217
drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022-2023 Linaro Ltd.
4
+
* Copyright (c) 2026 Luca Weiss <luca.weiss@fairphone.com>
5
+
*/
6
+
7
+
#include <linux/gpio/driver.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
11
+
#include "pinctrl-lpass-lpi.h"
12
+
13
+
enum lpass_lpi_functions {
14
+
LPI_MUX_dmic1_clk,
15
+
LPI_MUX_dmic1_data,
16
+
LPI_MUX_dmic2_clk,
17
+
LPI_MUX_dmic2_data,
18
+
LPI_MUX_dmic3_clk,
19
+
LPI_MUX_dmic3_data,
20
+
LPI_MUX_dmic4_clk,
21
+
LPI_MUX_dmic4_data,
22
+
LPI_MUX_i2s0_clk,
23
+
LPI_MUX_i2s0_data,
24
+
LPI_MUX_i2s0_ws,
25
+
LPI_MUX_i2s1_clk,
26
+
LPI_MUX_i2s1_data,
27
+
LPI_MUX_i2s1_ws,
28
+
LPI_MUX_i2s2_clk,
29
+
LPI_MUX_i2s2_data,
30
+
LPI_MUX_i2s2_ws,
31
+
LPI_MUX_i2s3_clk,
32
+
LPI_MUX_i2s3_data,
33
+
LPI_MUX_i2s3_ws,
34
+
LPI_MUX_qca_swr_clk,
35
+
LPI_MUX_qca_swr_data,
36
+
LPI_MUX_slimbus_clk,
37
+
LPI_MUX_slimbus_data,
38
+
LPI_MUX_swr_rx_clk,
39
+
LPI_MUX_swr_rx_data,
40
+
LPI_MUX_swr_tx_clk,
41
+
LPI_MUX_swr_tx_data,
42
+
LPI_MUX_wsa_swr_clk,
43
+
LPI_MUX_wsa_swr_data,
44
+
LPI_MUX_ext_mclk1_a,
45
+
LPI_MUX_ext_mclk1_b,
46
+
LPI_MUX_ext_mclk1_c,
47
+
LPI_MUX_ext_mclk1_d,
48
+
LPI_MUX_ext_mclk1_e,
49
+
LPI_MUX_gpio,
50
+
LPI_MUX__,
51
+
};
52
+
53
+
static const struct pinctrl_pin_desc milos_lpi_pins[] = {
54
+
PINCTRL_PIN(0, "gpio0"),
55
+
PINCTRL_PIN(1, "gpio1"),
56
+
PINCTRL_PIN(2, "gpio2"),
57
+
PINCTRL_PIN(3, "gpio3"),
58
+
PINCTRL_PIN(4, "gpio4"),
59
+
PINCTRL_PIN(5, "gpio5"),
60
+
PINCTRL_PIN(6, "gpio6"),
61
+
PINCTRL_PIN(7, "gpio7"),
62
+
PINCTRL_PIN(8, "gpio8"),
63
+
PINCTRL_PIN(9, "gpio9"),
64
+
PINCTRL_PIN(10, "gpio10"),
65
+
PINCTRL_PIN(11, "gpio11"),
66
+
PINCTRL_PIN(12, "gpio12"),
67
+
PINCTRL_PIN(13, "gpio13"),
68
+
PINCTRL_PIN(14, "gpio14"),
69
+
PINCTRL_PIN(15, "gpio15"),
70
+
PINCTRL_PIN(16, "gpio16"),
71
+
PINCTRL_PIN(17, "gpio17"),
72
+
PINCTRL_PIN(18, "gpio18"),
73
+
PINCTRL_PIN(19, "gpio19"),
74
+
PINCTRL_PIN(20, "gpio20"),
75
+
PINCTRL_PIN(21, "gpio21"),
76
+
PINCTRL_PIN(22, "gpio22"),
77
+
};
78
+
79
+
static const char * const gpio_groups[] = {
80
+
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
81
+
"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
82
+
"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
83
+
"gpio22",
84
+
};
85
+
86
+
static const char * const dmic1_clk_groups[] = { "gpio6" };
87
+
static const char * const dmic1_data_groups[] = { "gpio7" };
88
+
static const char * const dmic2_clk_groups[] = { "gpio8" };
89
+
static const char * const dmic2_data_groups[] = { "gpio9" };
90
+
static const char * const dmic3_clk_groups[] = { "gpio12" };
91
+
static const char * const dmic3_data_groups[] = { "gpio13" };
92
+
static const char * const dmic4_clk_groups[] = { "gpio21" };
93
+
static const char * const dmic4_data_groups[] = { "gpio22" };
94
+
static const char * const i2s0_clk_groups[] = { "gpio0" };
95
+
static const char * const i2s0_ws_groups[] = { "gpio1" };
96
+
static const char * const i2s0_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
97
+
static const char * const i2s1_clk_groups[] = { "gpio6" };
98
+
static const char * const i2s1_ws_groups[] = { "gpio7" };
99
+
static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
100
+
static const char * const i2s2_clk_groups[] = { "gpio10" };
101
+
static const char * const i2s2_ws_groups[] = { "gpio11" };
102
+
static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
103
+
static const char * const i2s3_clk_groups[] = { "gpio19" };
104
+
static const char * const i2s3_ws_groups[] = { "gpio20" };
105
+
static const char * const i2s3_data_groups[] = { "gpio21", "gpio22" };
106
+
static const char * const qca_swr_clk_groups[] = { "gpio19" };
107
+
static const char * const qca_swr_data_groups[] = { "gpio20" };
108
+
static const char * const slimbus_clk_groups[] = { "gpio19" };
109
+
static const char * const slimbus_data_groups[] = { "gpio20" };
110
+
static const char * const swr_rx_clk_groups[] = { "gpio3" };
111
+
static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
112
+
static const char * const swr_tx_clk_groups[] = { "gpio0" };
113
+
static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" };
114
+
static const char * const wsa_swr_clk_groups[] = { "gpio10" };
115
+
static const char * const wsa_swr_data_groups[] = { "gpio11" };
116
+
static const char * const ext_mclk1_a_groups[] = { "gpio13" };
117
+
static const char * const ext_mclk1_b_groups[] = { "gpio9" };
118
+
static const char * const ext_mclk1_c_groups[] = { "gpio5" };
119
+
static const char * const ext_mclk1_d_groups[] = { "gpio14" };
120
+
static const char * const ext_mclk1_e_groups[] = { "gpio22" };
121
+
122
+
static const struct lpi_pingroup milos_groups[] = {
123
+
LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _),
124
+
LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _),
125
+
LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _),
126
+
LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _),
127
+
LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _),
128
+
LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _),
129
+
LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _),
130
+
LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _),
131
+
LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _),
132
+
LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _),
133
+
LPI_PINGROUP(10, 16, wsa_swr_clk, i2s2_clk, _, _),
134
+
LPI_PINGROUP(11, 18, wsa_swr_data, i2s2_ws, _, _),
135
+
LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _),
136
+
LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _),
137
+
LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _),
138
+
/* gpio15 - gpio18 do not really exist */
139
+
LPI_PINGROUP(15, 20, _, _, _, _),
140
+
LPI_PINGROUP(16, 22, _, _, _, _),
141
+
LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
142
+
LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _),
143
+
LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _),
144
+
LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _),
145
+
LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _),
146
+
LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _),
147
+
};
148
+
149
+
static const struct lpi_function milos_functions[] = {
150
+
LPI_FUNCTION(gpio),
151
+
LPI_FUNCTION(dmic1_clk),
152
+
LPI_FUNCTION(dmic1_data),
153
+
LPI_FUNCTION(dmic2_clk),
154
+
LPI_FUNCTION(dmic2_data),
155
+
LPI_FUNCTION(dmic3_clk),
156
+
LPI_FUNCTION(dmic3_data),
157
+
LPI_FUNCTION(dmic4_clk),
158
+
LPI_FUNCTION(dmic4_data),
159
+
LPI_FUNCTION(i2s0_clk),
160
+
LPI_FUNCTION(i2s0_data),
161
+
LPI_FUNCTION(i2s0_ws),
162
+
LPI_FUNCTION(i2s1_clk),
163
+
LPI_FUNCTION(i2s1_data),
164
+
LPI_FUNCTION(i2s1_ws),
165
+
LPI_FUNCTION(i2s2_clk),
166
+
LPI_FUNCTION(i2s2_data),
167
+
LPI_FUNCTION(i2s2_ws),
168
+
LPI_FUNCTION(i2s3_clk),
169
+
LPI_FUNCTION(i2s3_data),
170
+
LPI_FUNCTION(i2s3_ws),
171
+
LPI_FUNCTION(qca_swr_clk),
172
+
LPI_FUNCTION(qca_swr_data),
173
+
LPI_FUNCTION(slimbus_clk),
174
+
LPI_FUNCTION(slimbus_data),
175
+
LPI_FUNCTION(swr_rx_clk),
176
+
LPI_FUNCTION(swr_rx_data),
177
+
LPI_FUNCTION(swr_tx_clk),
178
+
LPI_FUNCTION(swr_tx_data),
179
+
LPI_FUNCTION(wsa_swr_clk),
180
+
LPI_FUNCTION(wsa_swr_data),
181
+
LPI_FUNCTION(ext_mclk1_a),
182
+
LPI_FUNCTION(ext_mclk1_b),
183
+
LPI_FUNCTION(ext_mclk1_c),
184
+
LPI_FUNCTION(ext_mclk1_d),
185
+
LPI_FUNCTION(ext_mclk1_e),
186
+
};
187
+
188
+
static const struct lpi_pinctrl_variant_data milos_lpi_data = {
189
+
.pins = milos_lpi_pins,
190
+
.npins = ARRAY_SIZE(milos_lpi_pins),
191
+
.groups = milos_groups,
192
+
.ngroups = ARRAY_SIZE(milos_groups),
193
+
.functions = milos_functions,
194
+
.nfunctions = ARRAY_SIZE(milos_functions),
195
+
};
196
+
197
+
static const struct of_device_id lpi_pinctrl_of_match[] = {
198
+
{
199
+
.compatible = "qcom,milos-lpass-lpi-pinctrl",
200
+
.data = &milos_lpi_data,
201
+
},
202
+
{ }
203
+
};
204
+
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
205
+
206
+
static struct platform_driver lpi_pinctrl_driver = {
207
+
.driver = {
208
+
.name = "qcom-milos-lpass-lpi-pinctrl",
209
+
.of_match_table = lpi_pinctrl_of_match,
210
+
},
211
+
.probe = lpi_pinctrl_probe,
212
+
.remove = lpi_pinctrl_remove,
213
+
};
214
+
215
+
module_platform_driver(lpi_pinctrl_driver);
216
+
MODULE_DESCRIPTION("Qualcomm Milos LPI GPIO pin control driver");
217
+
MODULE_LICENSE("GPL");
-3
drivers/pinctrl/qcom/pinctrl-milos.c
-3
drivers/pinctrl/qcom/pinctrl-milos.c
···
36
36
.io_reg = 0x4 + REG_SIZE * id, \
37
37
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
38
38
.intr_status_reg = 0xc + REG_SIZE * id, \
39
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
40
39
.mux_bit = 2, \
41
40
.pull_bit = 0, \
42
41
.drv_bit = 6, \
···
66
67
.io_reg = 0, \
67
68
.intr_cfg_reg = 0, \
68
69
.intr_status_reg = 0, \
69
-
.intr_target_reg = 0, \
70
70
.mux_bit = -1, \
71
71
.pull_bit = pull, \
72
72
.drv_bit = drv, \
···
90
92
.io_reg = io, \
91
93
.intr_cfg_reg = 0, \
92
94
.intr_status_reg = 0, \
93
-
.intr_target_reg = 0, \
94
95
.mux_bit = -1, \
95
96
.pull_bit = 3, \
96
97
.drv_bit = 0, \
+18
-2
drivers/pinctrl/qcom/pinctrl-msm.c
+18
-2
drivers/pinctrl/qcom/pinctrl-msm.c
···
98
98
MSM_ACCESSOR(io)
99
99
MSM_ACCESSOR(intr_cfg)
100
100
MSM_ACCESSOR(intr_status)
101
-
MSM_ACCESSOR(intr_target)
101
+
102
+
static u32 msm_readl_intr_target(struct msm_pinctrl *pctrl,
103
+
const struct msm_pingroup *g)
104
+
{
105
+
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
106
+
107
+
return readl(pctrl->regs[g->tile] + reg);
108
+
}
109
+
110
+
static void msm_writel_intr_target(u32 val, struct msm_pinctrl *pctrl,
111
+
const struct msm_pingroup *g)
112
+
{
113
+
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
114
+
115
+
writel(val, pctrl->regs[g->tile] + reg);
116
+
}
102
117
103
118
static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
104
119
const struct msm_pingroup *g)
···
1093
1078
intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
1094
1079
1095
1080
if (pctrl->intr_target_use_scm) {
1096
-
u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1081
+
u32 reg = g->intr_target_reg ? g->intr_target_reg : g->intr_cfg_reg;
1082
+
u32 addr = pctrl->phys_base[0] + reg;
1097
1083
int ret;
1098
1084
1099
1085
qcom_scm_io_readl(addr, &val);
+5
-1
drivers/pinctrl/qcom/pinctrl-msm.h
+5
-1
drivers/pinctrl/qcom/pinctrl-msm.h
···
52
52
* @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
53
53
* @intr_status_reg: Offset of the register holding the status bits for this group.
54
54
* @intr_target_reg: Offset of the register specifying routing of the interrupts
55
-
* from this group.
55
+
* from this group. On most SoCs this register is the same as
56
+
* @intr_cfg_reg; leaving this field as zero causes the driver
57
+
* to fall back to @intr_cfg_reg automatically. Only set this
58
+
* explicitly on older SoCs where the interrupt target routing
59
+
* lives in a separate register (e.g. APQ8064, MSM8960).
56
60
* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
57
61
* @pull_bit: Offset in @ctl_reg for the bias configuration.
58
62
* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
-2
drivers/pinctrl/qcom/pinctrl-msm8226.c
-2
drivers/pinctrl/qcom/pinctrl-msm8226.c
···
282
282
.io_reg = 0x1004 + 0x10 * id, \
283
283
.intr_cfg_reg = 0x1008 + 0x10 * id, \
284
284
.intr_status_reg = 0x100c + 0x10 * id, \
285
-
.intr_target_reg = 0x1008 + 0x10 * id, \
286
285
.mux_bit = 2, \
287
286
.pull_bit = 0, \
288
287
.drv_bit = 6, \
···
307
308
.io_reg = 0, \
308
309
.intr_cfg_reg = 0, \
309
310
.intr_status_reg = 0, \
310
-
.intr_target_reg = 0, \
311
311
.mux_bit = -1, \
312
312
.pull_bit = pull, \
313
313
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8909.c
-2
drivers/pinctrl/qcom/pinctrl-msm8909.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8916.c
-2
drivers/pinctrl/qcom/pinctrl-msm8916.c
···
307
307
.io_reg = 0x4 + 0x1000 * id, \
308
308
.intr_cfg_reg = 0x8 + 0x1000 * id, \
309
309
.intr_status_reg = 0xc + 0x1000 * id, \
310
-
.intr_target_reg = 0x8 + 0x1000 * id, \
311
310
.mux_bit = 2, \
312
311
.pull_bit = 0, \
313
312
.drv_bit = 6, \
···
332
333
.io_reg = 0, \
333
334
.intr_cfg_reg = 0, \
334
335
.intr_status_reg = 0, \
335
-
.intr_target_reg = 0, \
336
336
.mux_bit = -1, \
337
337
.pull_bit = pull, \
338
338
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8917.c
-2
drivers/pinctrl/qcom/pinctrl-msm8917.c
···
333
333
.io_reg = 0x4 + 0x1000 * id, \
334
334
.intr_cfg_reg = 0x8 + 0x1000 * id, \
335
335
.intr_status_reg = 0xc + 0x1000 * id, \
336
-
.intr_target_reg = 0x8 + 0x1000 * id, \
337
336
.mux_bit = 2, \
338
337
.pull_bit = 0, \
339
338
.drv_bit = 6, \
···
358
359
.io_reg = 0, \
359
360
.intr_cfg_reg = 0, \
360
361
.intr_status_reg = 0, \
361
-
.intr_target_reg = 0, \
362
362
.mux_bit = -1, \
363
363
.pull_bit = pull, \
364
364
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8953.c
-2
drivers/pinctrl/qcom/pinctrl-msm8953.c
···
29
29
.io_reg = 0x4 + 0x1000 * id, \
30
30
.intr_cfg_reg = 0x8 + 0x1000 * id, \
31
31
.intr_status_reg = 0xc + 0x1000 * id, \
32
-
.intr_target_reg = 0x8 + 0x1000 * id, \
33
32
.mux_bit = 2, \
34
33
.pull_bit = 0, \
35
34
.drv_bit = 6, \
···
54
55
.io_reg = 0, \
55
56
.intr_cfg_reg = 0, \
56
57
.intr_status_reg = 0, \
57
-
.intr_target_reg = 0, \
58
58
.mux_bit = -1, \
59
59
.pull_bit = pull, \
60
60
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8976.c
-2
drivers/pinctrl/qcom/pinctrl-msm8976.c
···
35
35
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36
36
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37
37
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
39
38
.mux_bit = 2, \
40
39
.pull_bit = 0, \
41
40
.drv_bit = 6, \
···
60
61
.io_reg = 0, \
61
62
.intr_cfg_reg = 0, \
62
63
.intr_status_reg = 0, \
63
-
.intr_target_reg = 0, \
64
64
.mux_bit = -1, \
65
65
.pull_bit = pull, \
66
66
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8994.c
-2
drivers/pinctrl/qcom/pinctrl-msm8994.c
···
33
33
.io_reg = 0x1004 + 0x10 * id, \
34
34
.intr_cfg_reg = 0x1008 + 0x10 * id, \
35
35
.intr_status_reg = 0x100c + 0x10 * id, \
36
-
.intr_target_reg = 0x1008 + 0x10 * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
-2
drivers/pinctrl/qcom/pinctrl-msm8996.c
-2
drivers/pinctrl/qcom/pinctrl-msm8996.c
···
33
33
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-msm8998.c
-3
drivers/pinctrl/qcom/pinctrl-msm8998.c
···
35
35
.io_reg = base + 0x4 + 0x1000 * id, \
36
36
.intr_cfg_reg = base + 0x8 + 0x1000 * id, \
37
37
.intr_status_reg = base + 0xc + 0x1000 * id, \
38
-
.intr_target_reg = base + 0x8 + 0x1000 * id, \
39
38
.mux_bit = 2, \
40
39
.pull_bit = 0, \
41
40
.drv_bit = 6, \
···
60
61
.io_reg = 0, \
61
62
.intr_cfg_reg = 0, \
62
63
.intr_status_reg = 0, \
63
-
.intr_target_reg = 0, \
64
64
.mux_bit = -1, \
65
65
.pull_bit = pull, \
66
66
.drv_bit = drv, \
···
84
86
.io_reg = offset + 0x4, \
85
87
.intr_cfg_reg = 0, \
86
88
.intr_status_reg = 0, \
87
-
.intr_target_reg = 0, \
88
89
.mux_bit = -1, \
89
90
.pull_bit = 3, \
90
91
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-msm8x74.c
-3
drivers/pinctrl/qcom/pinctrl-msm8x74.c
···
344
344
.io_reg = 0x1004 + 0x10 * id, \
345
345
.intr_cfg_reg = 0x1008 + 0x10 * id, \
346
346
.intr_status_reg = 0x100c + 0x10 * id, \
347
-
.intr_target_reg = 0x1008 + 0x10 * id, \
348
347
.mux_bit = 2, \
349
348
.pull_bit = 0, \
350
349
.drv_bit = 6, \
···
369
370
.io_reg = 0, \
370
371
.intr_cfg_reg = 0, \
371
372
.intr_status_reg = 0, \
372
-
.intr_target_reg = 0, \
373
373
.mux_bit = -1, \
374
374
.pull_bit = pull, \
375
375
.drv_bit = drv, \
···
399
401
.io_reg = 0, \
400
402
.intr_cfg_reg = 0, \
401
403
.intr_status_reg = 0, \
402
-
.intr_target_reg = 0, \
403
404
.mux_bit = 25, \
404
405
.pull_bit = -1, \
405
406
.drv_bit = -1, \
-3
drivers/pinctrl/qcom/pinctrl-qcm2290.c
-3
drivers/pinctrl/qcom/pinctrl-qcm2290.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
60
61
.io_reg = 0, \
61
62
.intr_cfg_reg = 0, \
62
63
.intr_status_reg = 0, \
63
-
.intr_target_reg = 0, \
64
64
.mux_bit = -1, \
65
65
.pull_bit = pull, \
66
66
.drv_bit = drv, \
···
84
86
.io_reg = offset + 0x4, \
85
87
.intr_cfg_reg = 0, \
86
88
.intr_status_reg = 0, \
87
-
.intr_target_reg = 0, \
88
89
.mux_bit = -1, \
89
90
.pull_bit = 3, \
90
91
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-qcs404.c
-2
drivers/pinctrl/qcom/pinctrl-qcs404.c
···
43
43
.io_reg = 0x1000 * id + 0x4, \
44
44
.intr_cfg_reg = 0x1000 * id + 0x8, \
45
45
.intr_status_reg = 0x1000 * id + 0xc, \
46
-
.intr_target_reg = 0x1000 * id + 0x8, \
47
46
.tile = _tile, \
48
47
.mux_bit = 2, \
49
48
.pull_bit = 0, \
···
69
70
.io_reg = 0, \
70
71
.intr_cfg_reg = 0, \
71
72
.intr_status_reg = 0, \
72
-
.intr_target_reg = 0, \
73
73
.tile = SOUTH, \
74
74
.mux_bit = -1, \
75
75
.pull_bit = pull, \
-3
drivers/pinctrl/qcom/pinctrl-qcs615.c
-3
drivers/pinctrl/qcom/pinctrl-qcs615.c
···
43
43
.io_reg = 0x1000 * id + 0x4, \
44
44
.intr_cfg_reg = 0x1000 * id + 0x8, \
45
45
.intr_status_reg = 0x1000 * id + 0xc, \
46
-
.intr_target_reg = 0x1000 * id + 0x8, \
47
46
.tile = _tile, \
48
47
.mux_bit = 2, \
49
48
.pull_bit = 0, \
···
69
70
.io_reg = 0, \
70
71
.intr_cfg_reg = 0, \
71
72
.intr_status_reg = 0, \
72
-
.intr_target_reg = 0, \
73
73
.tile = _tile, \
74
74
.mux_bit = -1, \
75
75
.pull_bit = pull, \
···
94
96
.io_reg = offset + 0x4, \
95
97
.intr_cfg_reg = 0, \
96
98
.intr_status_reg = 0, \
97
-
.intr_target_reg = 0, \
98
99
.tile = WEST, \
99
100
.mux_bit = -1, \
100
101
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-qcs8300.c
-3
drivers/pinctrl/qcom/pinctrl-qcs8300.c
···
34
34
.io_reg = 0x4 + REG_SIZE * id, \
35
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
36
.intr_status_reg = 0xc + REG_SIZE * id, \
37
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
61
62
.io_reg = 0, \
62
63
.intr_cfg_reg = 0, \
63
64
.intr_status_reg = 0, \
64
-
.intr_target_reg = 0, \
65
65
.mux_bit = -1, \
66
66
.pull_bit = pull, \
67
67
.drv_bit = drv, \
···
85
87
.io_reg = offset + 0x4, \
86
88
.intr_cfg_reg = 0, \
87
89
.intr_status_reg = 0, \
88
-
.intr_target_reg = 0, \
89
90
.mux_bit = -1, \
90
91
.pull_bit = 3, \
91
92
.drv_bit = 0, \
-1
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
-1
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
···
106
106
groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
107
107
groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
108
108
groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
109
-
groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
110
109
111
110
groups[gpio].mux_bit = 2;
112
111
groups[gpio].pull_bit = 0;
-3
drivers/pinctrl/qcom/pinctrl-qdu1000.c
-3
drivers/pinctrl/qcom/pinctrl-qdu1000.c
···
35
35
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36
36
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37
37
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
39
38
.mux_bit = 2, \
40
39
.pull_bit = 0, \
41
40
.drv_bit = 6, \
···
60
61
.io_reg = 0, \
61
62
.intr_cfg_reg = 0, \
62
63
.intr_status_reg = 0, \
63
-
.intr_target_reg = 0, \
64
64
.mux_bit = -1, \
65
65
.pull_bit = pull, \
66
66
.drv_bit = drv, \
···
84
86
.io_reg = offset + 0x4, \
85
87
.intr_cfg_reg = 0, \
86
88
.intr_status_reg = 0, \
87
-
.intr_target_reg = 0, \
88
89
.mux_bit = -1, \
89
90
.pull_bit = 3, \
90
91
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sa8775p.c
-3
drivers/pinctrl/qcom/pinctrl-sa8775p.c
···
34
34
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
35
35
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
36
36
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
37
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
62
63
.io_reg = 0, \
63
64
.intr_cfg_reg = 0, \
64
65
.intr_status_reg = 0, \
65
-
.intr_target_reg = 0, \
66
66
.mux_bit = -1, \
67
67
.pull_bit = pull, \
68
68
.drv_bit = drv, \
···
86
88
.io_reg = offset + 0x4, \
87
89
.intr_cfg_reg = 0, \
88
90
.intr_status_reg = 0, \
89
-
.intr_target_reg = 0, \
90
91
.mux_bit = -1, \
91
92
.pull_bit = 3, \
92
93
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sar2130p.c
-2
drivers/pinctrl/qcom/pinctrl-sar2130p.c
···
34
34
.io_reg = 0x4 + REG_SIZE * id, \
35
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
36
.intr_status_reg = 0xc + REG_SIZE * id, \
37
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
61
62
.io_reg = 0, \
62
63
.intr_cfg_reg = 0, \
63
64
.intr_status_reg = 0, \
64
-
.intr_target_reg = 0, \
65
65
.mux_bit = -1, \
66
66
.pull_bit = pull, \
67
67
.drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sc7180.c
-3
drivers/pinctrl/qcom/pinctrl-sc7180.c
···
41
41
.io_reg = 0x1000 * id + 0x4, \
42
42
.intr_cfg_reg = 0x1000 * id + 0x8, \
43
43
.intr_status_reg = 0x1000 * id + 0xc, \
44
-
.intr_target_reg = 0x1000 * id + 0x8, \
45
44
.tile = _tile, \
46
45
.mux_bit = 2, \
47
46
.pull_bit = 0, \
···
67
68
.io_reg = 0, \
68
69
.intr_cfg_reg = 0, \
69
70
.intr_status_reg = 0, \
70
-
.intr_target_reg = 0, \
71
71
.tile = SOUTH, \
72
72
.mux_bit = -1, \
73
73
.pull_bit = pull, \
···
92
94
.io_reg = offset + 0x4, \
93
95
.intr_cfg_reg = 0, \
94
96
.intr_status_reg = 0, \
95
-
.intr_target_reg = 0, \
96
97
.tile = SOUTH, \
97
98
.mux_bit = -1, \
98
99
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sc7280.c
-3
drivers/pinctrl/qcom/pinctrl-sc7280.c
···
31
31
.io_reg = 0x1000 * id + 0x4, \
32
32
.intr_cfg_reg = 0x1000 * id + 0x8, \
33
33
.intr_status_reg = 0x1000 * id + 0xc, \
34
-
.intr_target_reg = 0x1000 * id + 0x8, \
35
34
.mux_bit = 2, \
36
35
.pull_bit = 0, \
37
36
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
···
82
84
.io_reg = offset + 0x4, \
83
85
.intr_cfg_reg = 0, \
84
86
.intr_status_reg = 0, \
85
-
.intr_target_reg = 0, \
86
87
.mux_bit = -1, \
87
88
.pull_bit = 3, \
88
89
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sc8180x.c
-3
drivers/pinctrl/qcom/pinctrl-sc8180x.c
···
60
60
.io_reg = REG_SIZE * id + 0x4 + offset, \
61
61
.intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \
62
62
.intr_status_reg = REG_SIZE * id + 0xc + offset,\
63
-
.intr_target_reg = REG_SIZE * id + 0x8 + offset,\
64
63
.tile = _tile, \
65
64
.mux_bit = 2, \
66
65
.pull_bit = 0, \
···
89
90
.io_reg = 0, \
90
91
.intr_cfg_reg = 0, \
91
92
.intr_status_reg = 0, \
92
-
.intr_target_reg = 0, \
93
93
.tile = EAST, \
94
94
.mux_bit = -1, \
95
95
.pull_bit = pull, \
···
114
116
.io_reg = 0xb6004, \
115
117
.intr_cfg_reg = 0, \
116
118
.intr_status_reg = 0, \
117
-
.intr_target_reg = 0, \
118
119
.tile = SOUTH, \
119
120
.mux_bit = -1, \
120
121
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
-3
drivers/pinctrl/qcom/pinctrl-sc8280xp.c
···
31
31
.io_reg = 0x4 + REG_SIZE * id, \
32
32
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
33
33
.intr_status_reg = 0xc + REG_SIZE * id, \
34
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
35
34
.mux_bit = 2, \
36
35
.pull_bit = 0, \
37
36
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
···
82
84
.io_reg = offset + 0x4, \
83
85
.intr_cfg_reg = 0, \
84
86
.intr_status_reg = 0, \
85
-
.intr_target_reg = 0, \
86
87
.mux_bit = -1, \
87
88
.pull_bit = 3, \
88
89
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdm660.c
-2
drivers/pinctrl/qcom/pinctrl-sdm660.c
···
46
46
.io_reg = 0x4 + REG_SIZE * id, \
47
47
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
48
48
.intr_status_reg = 0xc + REG_SIZE * id, \
49
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
50
49
.tile = _tile, \
51
50
.mux_bit = 2, \
52
51
.pull_bit = 0, \
···
72
73
.io_reg = 0, \
73
74
.intr_cfg_reg = 0, \
74
75
.intr_status_reg = 0, \
75
-
.intr_target_reg = 0, \
76
76
.tile = NORTH, \
77
77
.mux_bit = -1, \
78
78
.pull_bit = pull, \
+166
drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c
+166
drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2023-2026, Richard Acayan. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/kernel.h>
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pinctrl/pinctrl.h>
11
+
12
+
#include "pinctrl-lpass-lpi.h"
13
+
14
+
enum lpass_lpi_functions {
15
+
LPI_MUX_comp_rx,
16
+
LPI_MUX_dmic1_clk,
17
+
LPI_MUX_dmic1_data,
18
+
LPI_MUX_dmic2_clk,
19
+
LPI_MUX_dmic2_data,
20
+
LPI_MUX_i2s1_clk,
21
+
LPI_MUX_i2s1_data,
22
+
LPI_MUX_i2s1_ws,
23
+
LPI_MUX_lpi_cdc_rst,
24
+
LPI_MUX_mclk0,
25
+
LPI_MUX_pdm_rx,
26
+
LPI_MUX_pdm_sync,
27
+
LPI_MUX_pdm_tx,
28
+
LPI_MUX_slimbus_clk,
29
+
LPI_MUX_gpio,
30
+
LPI_MUX__,
31
+
};
32
+
33
+
static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = {
34
+
PINCTRL_PIN(0, "gpio0"),
35
+
PINCTRL_PIN(1, "gpio1"),
36
+
PINCTRL_PIN(2, "gpio2"),
37
+
PINCTRL_PIN(3, "gpio3"),
38
+
PINCTRL_PIN(4, "gpio4"),
39
+
PINCTRL_PIN(5, "gpio5"),
40
+
PINCTRL_PIN(6, "gpio6"),
41
+
PINCTRL_PIN(7, "gpio7"),
42
+
PINCTRL_PIN(8, "gpio8"),
43
+
PINCTRL_PIN(9, "gpio9"),
44
+
PINCTRL_PIN(10, "gpio10"),
45
+
PINCTRL_PIN(11, "gpio11"),
46
+
PINCTRL_PIN(12, "gpio12"),
47
+
PINCTRL_PIN(13, "gpio13"),
48
+
PINCTRL_PIN(14, "gpio14"),
49
+
PINCTRL_PIN(15, "gpio15"),
50
+
PINCTRL_PIN(16, "gpio16"),
51
+
PINCTRL_PIN(17, "gpio17"),
52
+
PINCTRL_PIN(18, "gpio18"),
53
+
PINCTRL_PIN(19, "gpio19"),
54
+
PINCTRL_PIN(20, "gpio20"),
55
+
PINCTRL_PIN(21, "gpio21"),
56
+
PINCTRL_PIN(22, "gpio22"),
57
+
PINCTRL_PIN(23, "gpio23"),
58
+
PINCTRL_PIN(24, "gpio24"),
59
+
PINCTRL_PIN(25, "gpio25"),
60
+
PINCTRL_PIN(26, "gpio26"),
61
+
PINCTRL_PIN(27, "gpio27"),
62
+
PINCTRL_PIN(28, "gpio28"),
63
+
PINCTRL_PIN(29, "gpio29"),
64
+
PINCTRL_PIN(30, "gpio30"),
65
+
PINCTRL_PIN(31, "gpio31"),
66
+
};
67
+
68
+
static const char * const comp_rx_groups[] = { "gpio22", "gpio24" };
69
+
static const char * const dmic1_clk_groups[] = { "gpio26" };
70
+
static const char * const dmic1_data_groups[] = { "gpio27" };
71
+
static const char * const dmic2_clk_groups[] = { "gpio28" };
72
+
static const char * const dmic2_data_groups[] = { "gpio29" };
73
+
static const char * const i2s1_clk_groups[] = { "gpio8" };
74
+
static const char * const i2s1_ws_groups[] = { "gpio9" };
75
+
static const char * const i2s1_data_groups[] = { "gpio10", "gpio11" };
76
+
static const char * const lpi_cdc_rst_groups[] = { "gpio29" };
77
+
static const char * const mclk0_groups[] = { "gpio19" };
78
+
static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
79
+
static const char * const pdm_sync_groups[] = { "gpio19" };
80
+
static const char * const pdm_tx_groups[] = { "gpio20" };
81
+
static const char * const slimbus_clk_groups[] = { "gpio18" };
82
+
83
+
static const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {
84
+
LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
85
+
LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
86
+
LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
87
+
LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
88
+
LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
89
+
LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
90
+
LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
91
+
LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
92
+
LPI_PINGROUP(8, LPI_NO_SLEW, _, _, i2s1_clk, _),
93
+
LPI_PINGROUP(9, LPI_NO_SLEW, _, _, i2s1_ws, _),
94
+
LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, i2s1_data),
95
+
LPI_PINGROUP(11, LPI_NO_SLEW, _, i2s1_data, _, _),
96
+
LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
97
+
LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
98
+
LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
99
+
LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
100
+
LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
101
+
LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
102
+
LPI_PINGROUP(18, LPI_NO_SLEW, _, slimbus_clk, _, _),
103
+
LPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _),
104
+
LPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _),
105
+
LPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _),
106
+
LPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _),
107
+
LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),
108
+
LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),
109
+
LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),
110
+
LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _),
111
+
LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _),
112
+
LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _),
113
+
LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _),
114
+
LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),
115
+
LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),
116
+
};
117
+
118
+
static const struct lpi_function sdm670_lpi_pinctrl_functions[] = {
119
+
LPI_FUNCTION(comp_rx),
120
+
LPI_FUNCTION(dmic1_clk),
121
+
LPI_FUNCTION(dmic1_data),
122
+
LPI_FUNCTION(dmic2_clk),
123
+
LPI_FUNCTION(dmic2_data),
124
+
LPI_FUNCTION(i2s1_clk),
125
+
LPI_FUNCTION(i2s1_data),
126
+
LPI_FUNCTION(i2s1_ws),
127
+
LPI_FUNCTION(lpi_cdc_rst),
128
+
LPI_FUNCTION(mclk0),
129
+
LPI_FUNCTION(pdm_tx),
130
+
LPI_FUNCTION(pdm_rx),
131
+
LPI_FUNCTION(pdm_sync),
132
+
LPI_FUNCTION(slimbus_clk),
133
+
};
134
+
135
+
static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = {
136
+
.pins = sdm670_lpi_pinctrl_pins,
137
+
.npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins),
138
+
.groups = sdm670_lpi_pinctrl_groups,
139
+
.ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups),
140
+
.functions = sdm670_lpi_pinctrl_functions,
141
+
.nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions),
142
+
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
143
+
};
144
+
145
+
static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = {
146
+
{
147
+
.compatible = "qcom,sdm670-lpass-lpi-pinctrl",
148
+
.data = &sdm670_lpi_pinctrl_data,
149
+
},
150
+
{ }
151
+
};
152
+
MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);
153
+
154
+
static struct platform_driver sdm670_lpi_pinctrl_driver = {
155
+
.driver = {
156
+
.name = "qcom-sdm670-lpass-lpi-pinctrl",
157
+
.of_match_table = sdm670_lpi_pinctrl_of_match,
158
+
},
159
+
.probe = lpi_pinctrl_probe,
160
+
.remove = lpi_pinctrl_remove,
161
+
};
162
+
module_platform_driver(sdm670_lpi_pinctrl_driver);
163
+
164
+
MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>");
165
+
MODULE_DESCRIPTION("QTI SDM670 LPI GPIO pin control driver");
166
+
MODULE_LICENSE("GPL");
-4
drivers/pinctrl/qcom/pinctrl-sdm670.c
-4
drivers/pinctrl/qcom/pinctrl-sdm670.c
···
37
37
.io_reg = base + 0x4 + REG_SIZE * id, \
38
38
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
39
39
.intr_status_reg = base + 0xc + REG_SIZE * id, \
40
-
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
41
40
.mux_bit = 2, \
42
41
.pull_bit = 0, \
43
42
.drv_bit = 6, \
···
66
67
.io_reg = 0, \
67
68
.intr_cfg_reg = 0, \
68
69
.intr_status_reg = 0, \
69
-
.intr_target_reg = 0, \
70
70
.mux_bit = -1, \
71
71
.pull_bit = -1, \
72
72
.drv_bit = -1, \
···
90
92
.io_reg = 0, \
91
93
.intr_cfg_reg = 0, \
92
94
.intr_status_reg = 0, \
93
-
.intr_target_reg = 0, \
94
95
.mux_bit = -1, \
95
96
.pull_bit = pull, \
96
97
.drv_bit = drv, \
···
114
117
.io_reg = offset + 0x4, \
115
118
.intr_cfg_reg = 0, \
116
119
.intr_status_reg = 0, \
117
-
.intr_target_reg = 0, \
118
120
.mux_bit = -1, \
119
121
.pull_bit = 3, \
120
122
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sdm845.c
-3
drivers/pinctrl/qcom/pinctrl-sdm845.c
···
37
37
.io_reg = base + 0x4 + REG_SIZE * id, \
38
38
.intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
39
39
.intr_status_reg = base + 0xc + REG_SIZE * id, \
40
-
.intr_target_reg = base + 0x8 + REG_SIZE * id, \
41
40
.mux_bit = 2, \
42
41
.pull_bit = 0, \
43
42
.drv_bit = 6, \
···
62
63
.io_reg = 0, \
63
64
.intr_cfg_reg = 0, \
64
65
.intr_status_reg = 0, \
65
-
.intr_target_reg = 0, \
66
66
.mux_bit = -1, \
67
67
.pull_bit = pull, \
68
68
.drv_bit = drv, \
···
86
88
.io_reg = offset + 0x4, \
87
89
.intr_cfg_reg = 0, \
88
90
.intr_status_reg = 0, \
89
-
.intr_target_reg = 0, \
90
91
.mux_bit = -1, \
91
92
.pull_bit = 3, \
92
93
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdx55.c
-2
drivers/pinctrl/qcom/pinctrl-sdx55.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sdx65.c
-3
drivers/pinctrl/qcom/pinctrl-sdx65.c
···
33
33
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
···
82
84
.io_reg = offset + 0x4, \
83
85
.intr_cfg_reg = 0, \
84
86
.intr_status_reg = 0, \
85
-
.intr_target_reg = 0, \
86
87
.mux_bit = -1, \
87
88
.pull_bit = 3, \
88
89
.drv_bit = 0, \
-2
drivers/pinctrl/qcom/pinctrl-sdx75.c
-2
drivers/pinctrl/qcom/pinctrl-sdx75.c
···
19
19
.io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
20
20
.intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
21
21
.intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
22
-
.intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
23
22
.mux_bit = 2, \
24
23
.pull_bit = 0, \
25
24
.drv_bit = 6, \
···
59
60
.io_reg = 0, \
60
61
.intr_cfg_reg = 0, \
61
62
.intr_status_reg = 0, \
62
-
.intr_target_reg = 0, \
63
63
.mux_bit = -1, \
64
64
.pull_bit = pull, \
65
65
.drv_bit = drv, \
-3
drivers/pinctrl/qcom/pinctrl-sm4450.c
-3
drivers/pinctrl/qcom/pinctrl-sm4450.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
60
61
.io_reg = 0, \
61
62
.intr_cfg_reg = 0, \
62
63
.intr_status_reg = 0, \
63
-
.intr_target_reg = 0, \
64
64
.mux_bit = -1, \
65
65
.pull_bit = pull, \
66
66
.drv_bit = drv, \
···
84
86
.io_reg = offset + 0x4, \
85
87
.intr_cfg_reg = 0, \
86
88
.intr_status_reg = 0, \
87
-
.intr_target_reg = 0, \
88
89
.mux_bit = -1, \
89
90
.pull_bit = 3, \
90
91
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm6115.c
-3
drivers/pinctrl/qcom/pinctrl-sm6115.c
···
43
43
.io_reg = 0x4 + 0x1000 * id, \
44
44
.intr_cfg_reg = 0x8 + 0x1000 * id, \
45
45
.intr_status_reg = 0xc + 0x1000 * id, \
46
-
.intr_target_reg = 0x8 + 0x1000 * id, \
47
46
.tile = _tile, \
48
47
.mux_bit = 2, \
49
48
.pull_bit = 0, \
···
69
70
.io_reg = 0, \
70
71
.intr_cfg_reg = 0, \
71
72
.intr_status_reg = 0, \
72
-
.intr_target_reg = 0, \
73
73
.tile = _tile, \
74
74
.mux_bit = -1, \
75
75
.pull_bit = pull, \
···
94
96
.io_reg = offset + 0x4, \
95
97
.intr_cfg_reg = 0, \
96
98
.intr_status_reg = 0, \
97
-
.intr_target_reg = 0, \
98
99
.tile = WEST, \
99
100
.mux_bit = -1, \
100
101
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm6125.c
-3
drivers/pinctrl/qcom/pinctrl-sm6125.c
···
40
40
.io_reg = 0x4 + 0x1000 * id, \
41
41
.intr_cfg_reg = 0x8 + 0x1000 * id, \
42
42
.intr_status_reg = 0xc + 0x1000 * id, \
43
-
.intr_target_reg = 0x8 + 0x1000 * id, \
44
43
.tile = _tile, \
45
44
.mux_bit = 2, \
46
45
.pull_bit = 0, \
···
66
67
.io_reg = 0, \
67
68
.intr_cfg_reg = 0, \
68
69
.intr_status_reg = 0, \
69
-
.intr_target_reg = 0, \
70
70
.tile = _tile, \
71
71
.mux_bit = -1, \
72
72
.pull_bit = pull, \
···
91
93
.io_reg = offset + 0x4, \
92
94
.intr_cfg_reg = 0, \
93
95
.intr_status_reg = 0, \
94
-
.intr_target_reg = 0, \
95
96
.tile = WEST, \
96
97
.mux_bit = -1, \
97
98
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm6350.c
-3
drivers/pinctrl/qcom/pinctrl-sm6350.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
58
59
.io_reg = 0, \
59
60
.intr_cfg_reg = 0, \
60
61
.intr_status_reg = 0, \
61
-
.intr_target_reg = 0, \
62
62
.mux_bit = -1, \
63
63
.pull_bit = pull, \
64
64
.drv_bit = drv, \
···
82
84
.io_reg = offset + 0x4, \
83
85
.intr_cfg_reg = 0, \
84
86
.intr_status_reg = 0, \
85
-
.intr_target_reg = 0, \
86
87
.mux_bit = -1, \
87
88
.pull_bit = 3, \
88
89
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm6375.c
-3
drivers/pinctrl/qcom/pinctrl-sm6375.c
···
34
34
.io_reg = REG_SIZE * id + 0x4, \
35
35
.intr_cfg_reg = REG_SIZE * id + 0x8, \
36
36
.intr_status_reg = REG_SIZE * id + 0xc, \
37
-
.intr_target_reg = REG_SIZE * id + 0x8, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
61
62
.io_reg = 0, \
62
63
.intr_cfg_reg = 0, \
63
64
.intr_status_reg = 0, \
64
-
.intr_target_reg = 0, \
65
65
.mux_bit = -1, \
66
66
.pull_bit = pull, \
67
67
.drv_bit = drv, \
···
85
87
.io_reg = offset + 0x4, \
86
88
.intr_cfg_reg = 0, \
87
89
.intr_status_reg = 0, \
88
-
.intr_target_reg = 0, \
89
90
.mux_bit = -1, \
90
91
.pull_bit = 3, \
91
92
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm7150.c
-3
drivers/pinctrl/qcom/pinctrl-sm7150.c
···
47
47
.io_reg = 0x4 + REG_SIZE * id, \
48
48
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
49
49
.intr_status_reg = 0xc + REG_SIZE * id, \
50
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
51
50
.tile = _tile, \
52
51
.mux_bit = 2, \
53
52
.pull_bit = 0, \
···
73
74
.io_reg = 0, \
74
75
.intr_cfg_reg = 0, \
75
76
.intr_status_reg = 0, \
76
-
.intr_target_reg = 0, \
77
77
.tile = _tile, \
78
78
.mux_bit = -1, \
79
79
.pull_bit = pull, \
···
98
100
.io_reg = offset + 0x4, \
99
101
.intr_cfg_reg = 0, \
100
102
.intr_status_reg = 0, \
101
-
.intr_target_reg = 0, \
102
103
.tile = WEST, \
103
104
.mux_bit = -1, \
104
105
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8150.c
-3
drivers/pinctrl/qcom/pinctrl-sm8150.c
···
43
43
.io_reg = 0x1000 * id + 0x4, \
44
44
.intr_cfg_reg = 0x1000 * id + 0x8, \
45
45
.intr_status_reg = 0x1000 * id + 0xc, \
46
-
.intr_target_reg = 0x1000 * id + 0x8, \
47
46
.tile = _tile, \
48
47
.mux_bit = 2, \
49
48
.pull_bit = 0, \
···
69
70
.io_reg = 0, \
70
71
.intr_cfg_reg = 0, \
71
72
.intr_status_reg = 0, \
72
-
.intr_target_reg = 0, \
73
73
.tile = NORTH, \
74
74
.mux_bit = -1, \
75
75
.pull_bit = pull, \
···
94
96
.io_reg = offset + 0x4, \
95
97
.intr_cfg_reg = 0, \
96
98
.intr_status_reg = 0, \
97
-
.intr_target_reg = 0, \
98
99
.tile = SOUTH, \
99
100
.mux_bit = -1, \
100
101
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8250.c
-3
drivers/pinctrl/qcom/pinctrl-sm8250.c
···
44
44
.io_reg = REG_SIZE * id + 0x4, \
45
45
.intr_cfg_reg = REG_SIZE * id + 0x8, \
46
46
.intr_status_reg = REG_SIZE * id + 0xc, \
47
-
.intr_target_reg = REG_SIZE * id + 0x8, \
48
47
.tile = _tile, \
49
48
.mux_bit = 2, \
50
49
.pull_bit = 0, \
···
72
73
.io_reg = 0, \
73
74
.intr_cfg_reg = 0, \
74
75
.intr_status_reg = 0, \
75
-
.intr_target_reg = 0, \
76
76
.tile = NORTH, \
77
77
.mux_bit = -1, \
78
78
.pull_bit = pull, \
···
97
99
.io_reg = offset + 0x4, \
98
100
.intr_cfg_reg = 0, \
99
101
.intr_status_reg = 0, \
100
-
.intr_target_reg = 0, \
101
102
.tile = SOUTH, \
102
103
.mux_bit = -1, \
103
104
.pull_bit = 3, \
-3
drivers/pinctrl/qcom/pinctrl-sm8350.c
-3
drivers/pinctrl/qcom/pinctrl-sm8350.c
···
34
34
.io_reg = REG_SIZE * id + 0x4, \
35
35
.intr_cfg_reg = REG_SIZE * id + 0x8, \
36
36
.intr_status_reg = REG_SIZE * id + 0xc, \
37
-
.intr_target_reg = REG_SIZE * id + 0x8, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
59
60
.io_reg = 0, \
60
61
.intr_cfg_reg = 0, \
61
62
.intr_status_reg = 0, \
62
-
.intr_target_reg = 0, \
63
63
.mux_bit = -1, \
64
64
.pull_bit = pull, \
65
65
.drv_bit = drv, \
···
83
85
.io_reg = offset + 0x4, \
84
86
.intr_cfg_reg = 0, \
85
87
.intr_status_reg = 0, \
86
-
.intr_target_reg = 0, \
87
88
.mux_bit = -1, \
88
89
.pull_bit = 3, \
89
90
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8450.c
-3
drivers/pinctrl/qcom/pinctrl-sm8450.c
···
34
34
.io_reg = 0x4 + REG_SIZE * id, \
35
35
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
36
36
.intr_status_reg = 0xc + REG_SIZE * id, \
37
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
38
37
.mux_bit = 2, \
39
38
.pull_bit = 0, \
40
39
.drv_bit = 6, \
···
61
62
.io_reg = 0, \
62
63
.intr_cfg_reg = 0, \
63
64
.intr_status_reg = 0, \
64
-
.intr_target_reg = 0, \
65
65
.mux_bit = -1, \
66
66
.pull_bit = pull, \
67
67
.drv_bit = drv, \
···
85
87
.io_reg = offset + 0x4, \
86
88
.intr_cfg_reg = 0, \
87
89
.intr_status_reg = 0, \
88
-
.intr_target_reg = 0, \
89
90
.mux_bit = -1, \
90
91
.pull_bit = 3, \
91
92
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8550.c
-3
drivers/pinctrl/qcom/pinctrl-sm8550.c
···
35
35
.io_reg = 0x4 + REG_SIZE * id, \
36
36
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
37
37
.intr_status_reg = 0xc + REG_SIZE * id, \
38
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
39
38
.mux_bit = 2, \
40
39
.pull_bit = 0, \
41
40
.drv_bit = 6, \
···
63
64
.io_reg = 0, \
64
65
.intr_cfg_reg = 0, \
65
66
.intr_status_reg = 0, \
66
-
.intr_target_reg = 0, \
67
67
.mux_bit = -1, \
68
68
.pull_bit = pull, \
69
69
.drv_bit = drv, \
···
87
89
.io_reg = offset + 0x4, \
88
90
.intr_cfg_reg = 0, \
89
91
.intr_status_reg = 0, \
90
-
.intr_target_reg = 0, \
91
92
.mux_bit = -1, \
92
93
.pull_bit = 3, \
93
94
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8650.c
-3
drivers/pinctrl/qcom/pinctrl-sm8650.c
···
36
36
.io_reg = 0x4 + REG_SIZE * id, \
37
37
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
38
38
.intr_status_reg = 0xc + REG_SIZE * id, \
39
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
40
39
.mux_bit = 2, \
41
40
.pull_bit = 0, \
42
41
.drv_bit = 6, \
···
66
67
.io_reg = 0, \
67
68
.intr_cfg_reg = 0, \
68
69
.intr_status_reg = 0, \
69
-
.intr_target_reg = 0, \
70
70
.mux_bit = -1, \
71
71
.pull_bit = pull, \
72
72
.drv_bit = drv, \
···
90
92
.io_reg = io, \
91
93
.intr_cfg_reg = 0, \
92
94
.intr_status_reg = 0, \
93
-
.intr_target_reg = 0, \
94
95
.mux_bit = -1, \
95
96
.pull_bit = 3, \
96
97
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-sm8750.c
-3
drivers/pinctrl/qcom/pinctrl-sm8750.c
···
35
35
.io_reg = 0x4 + REG_SIZE * id, \
36
36
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
37
37
.intr_status_reg = 0xc + REG_SIZE * id, \
38
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
39
38
.mux_bit = 2, \
40
39
.pull_bit = 0, \
41
40
.drv_bit = 6, \
···
64
65
.io_reg = 0, \
65
66
.intr_cfg_reg = 0, \
66
67
.intr_status_reg = 0, \
67
-
.intr_target_reg = 0, \
68
68
.mux_bit = -1, \
69
69
.pull_bit = pull, \
70
70
.drv_bit = drv, \
···
88
90
.io_reg = io, \
89
91
.intr_cfg_reg = 0, \
90
92
.intr_status_reg = 0, \
91
-
.intr_target_reg = 0, \
92
93
.mux_bit = -1, \
93
94
.pull_bit = 3, \
94
95
.drv_bit = 0, \
-3
drivers/pinctrl/qcom/pinctrl-x1e80100.c
-3
drivers/pinctrl/qcom/pinctrl-x1e80100.c
···
33
33
.io_reg = 0x4 + REG_SIZE * id, \
34
34
.intr_cfg_reg = 0x8 + REG_SIZE * id, \
35
35
.intr_status_reg = 0xc + REG_SIZE * id, \
36
-
.intr_target_reg = 0x8 + REG_SIZE * id, \
37
36
.mux_bit = 2, \
38
37
.pull_bit = 0, \
39
38
.drv_bit = 6, \
···
61
62
.io_reg = 0, \
62
63
.intr_cfg_reg = 0, \
63
64
.intr_status_reg = 0, \
64
-
.intr_target_reg = 0, \
65
65
.mux_bit = -1, \
66
66
.pull_bit = pull, \
67
67
.drv_bit = drv, \
···
85
87
.io_reg = offset + 0x4, \
86
88
.intr_cfg_reg = 0, \
87
89
.intr_status_reg = 0, \
88
-
.intr_target_reg = 0, \
89
90
.mux_bit = -1, \
90
91
.pull_bit = 3, \
91
92
.drv_bit = 0, \
+14
drivers/pinctrl/realtek/Kconfig
+14
drivers/pinctrl/realtek/Kconfig
···
22
22
tristate "Realtek DHC 1315E pin controller driver"
23
23
depends on PINCTRL_RTD
24
24
default y
25
+
26
+
config PINCTRL_RTD1625
27
+
tristate "Realtek DHC 1625 pin controller driver"
28
+
depends on PINCTRL_RTD
29
+
default y
30
+
help
31
+
This driver enables support for the pin controller on the Realtek
32
+
RTD1625 SoCs.
33
+
34
+
It implements pin multiplexing for function selection and GPIO enabling.
35
+
It also utilizes the generic pin configuration interface to manage
36
+
electrical properties for both individual pins and pin groups.
37
+
38
+
Say Y here to enable the pinctrl driver for RTD1625 SoCs
+1
drivers/pinctrl/realtek/Makefile
+1
drivers/pinctrl/realtek/Makefile
+189
-35
drivers/pinctrl/realtek/pinctrl-rtd.c
+189
-35
drivers/pinctrl/realtek/pinctrl-rtd.c
···
30
30
struct pinctrl_desc desc;
31
31
const struct rtd_pinctrl_desc *info;
32
32
struct regmap *regmap_pinctrl;
33
+
u32 **saved_regs;
33
34
};
34
35
35
36
/* custom pinconf parameters */
36
37
#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1)
37
38
#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2)
38
39
#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)
40
+
#define RTD_HIGH_VIL (PIN_CONFIG_END + 4)
39
41
40
42
static const struct pinconf_generic_params rtd_custom_bindings[] = {
41
43
{"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0},
42
44
{"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0},
43
45
{"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
46
+
{"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0},
44
47
};
45
48
46
49
static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
···
282
279
static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
283
280
unsigned int pinnr,
284
281
enum pin_config_param param,
285
-
enum pin_config_param arg)
282
+
unsigned int arg)
286
283
{
287
284
const struct rtd_pin_config_desc *config_desc;
288
285
const struct rtd_pin_sconfig_desc *sconfig_desc;
···
290
287
u16 strength;
291
288
u32 val;
292
289
u32 mask;
293
-
u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off;
290
+
u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off,
291
+
input_volt_off, sr_off, hvil_off;
294
292
const char *name = data->info->pins[pinnr].name;
295
293
int ret = 0;
296
294
297
295
config_desc = rtd_pinctrl_find_config(data, pinnr);
298
296
if (!config_desc) {
299
-
dev_err(data->dev, "Not support pin config for pin: %s\n", name);
297
+
dev_err(data->dev, "Pin config unsupported for pin: %s\n", name);
300
298
return -ENOTSUPP;
301
299
}
302
300
switch ((u32)param) {
303
301
case PIN_CONFIG_INPUT_SCHMITT:
304
302
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
305
303
if (config_desc->smt_offset == NA) {
306
-
dev_err(data->dev, "Not support input schmitt for pin: %s\n", name);
304
+
dev_err(data->dev, "Input schmitt unsupported for pin: %s\n", name);
307
305
return -ENOTSUPP;
308
306
}
309
307
smt_off = config_desc->base_bit + config_desc->smt_offset;
···
317
313
318
314
case PIN_CONFIG_DRIVE_PUSH_PULL:
319
315
if (config_desc->pud_en_offset == NA) {
320
-
dev_err(data->dev, "Not support push pull for pin: %s\n", name);
316
+
dev_err(data->dev, "Push pull unsupported for pin: %s\n", name);
321
317
return -ENOTSUPP;
322
318
}
323
319
pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
···
329
325
330
326
case PIN_CONFIG_BIAS_DISABLE:
331
327
if (config_desc->pud_en_offset == NA) {
332
-
dev_err(data->dev, "Not support bias disable for pin: %s\n", name);
328
+
dev_err(data->dev, "Bias disable unsupported for pin: %s\n", name);
333
329
return -ENOTSUPP;
334
330
}
335
331
pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
···
341
337
342
338
case PIN_CONFIG_BIAS_PULL_UP:
343
339
if (config_desc->pud_en_offset == NA) {
344
-
dev_err(data->dev, "Not support bias pull up for pin:%s\n", name);
340
+
dev_err(data->dev, "Bias pull up unsupported for pin:%s\n", name);
345
341
return -ENOTSUPP;
346
342
}
347
343
pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
···
354
350
355
351
case PIN_CONFIG_BIAS_PULL_DOWN:
356
352
if (config_desc->pud_en_offset == NA) {
357
-
dev_err(data->dev, "Not support bias pull down for pin: %s\n", name);
353
+
dev_err(data->dev, "Bias pull down unsupported for pin: %s\n", name);
358
354
return -ENOTSUPP;
359
355
}
360
356
pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
···
388
384
return -EINVAL;
389
385
break;
390
386
case NA:
391
-
dev_err(data->dev, "Not support drive strength for pin: %s\n", name);
387
+
dev_err(data->dev, "Drive strength unsupported for pin: %s\n", name);
392
388
return -ENOTSUPP;
393
389
default:
394
390
return -EINVAL;
···
398
394
399
395
case PIN_CONFIG_POWER_SOURCE:
400
396
if (config_desc->power_offset == NA) {
401
-
dev_err(data->dev, "Not support power source for pin: %s\n", name);
397
+
dev_err(data->dev, "Power source unsupported for pin: %s\n", name);
402
398
return -ENOTSUPP;
403
399
}
404
400
reg_off = config_desc->reg_offset;
···
412
408
val = set_val ? mask : 0;
413
409
break;
414
410
411
+
case PIN_CONFIG_SLEW_RATE:
412
+
if (config_desc->slew_rate_offset == NA) {
413
+
dev_err(data->dev, "Slew rate setting unsupported for pin: %s\n", name);
414
+
return -ENOTSUPP;
415
+
}
416
+
417
+
switch (arg) {
418
+
case 1:
419
+
set_val = 0;
420
+
break;
421
+
case 10:
422
+
set_val = 1;
423
+
break;
424
+
case 20:
425
+
set_val = 2;
426
+
break;
427
+
case 30:
428
+
set_val = 3;
429
+
break;
430
+
default:
431
+
return -EINVAL;
432
+
}
433
+
434
+
sr_off = config_desc->base_bit + config_desc->slew_rate_offset;
435
+
reg_off = config_desc->reg_offset;
436
+
mask = 0x3 << sr_off;
437
+
val = arg << sr_off;
438
+
break;
439
+
440
+
case PIN_CONFIG_INPUT_VOLTAGE_UV:
441
+
if (config_desc->input_volt_offset == NA) {
442
+
dev_err(data->dev, "Input voltage level setting unsupported for pin:%s\n",
443
+
name);
444
+
return -ENOTSUPP;
445
+
}
446
+
447
+
if (arg == 3300000)
448
+
set_val = 1;
449
+
else if (arg == 1800000)
450
+
set_val = 0;
451
+
else
452
+
return -EINVAL;
453
+
454
+
input_volt_off = config_desc->base_bit + config_desc->input_volt_offset;
455
+
reg_off = config_desc->reg_offset;
456
+
457
+
mask = BIT(input_volt_off);
458
+
val = set_val ? BIT(input_volt_off) : 0;
459
+
break;
460
+
461
+
case RTD_HIGH_VIL:
462
+
if (config_desc->hvil_offset == NA) {
463
+
dev_err(data->dev, "High vil setting unsupported for pin:%s\n", name);
464
+
return -ENOTSUPP;
465
+
}
466
+
hvil_off = config_desc->base_bit + config_desc->hvil_offset;
467
+
reg_off = config_desc->reg_offset;
468
+
mask = BIT(hvil_off);
469
+
val = 1;
470
+
break;
471
+
415
472
case RTD_DRIVE_STRENGH_P:
416
473
sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
417
474
if (!sconfig_desc) {
418
-
dev_err(data->dev, "Not support P driving for pin: %s\n", name);
475
+
dev_err(data->dev, "P driving unsupported for pin: %s\n", name);
419
476
return -ENOTSUPP;
420
477
}
421
478
set_val = arg;
···
493
428
case RTD_DRIVE_STRENGH_N:
494
429
sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
495
430
if (!sconfig_desc) {
496
-
dev_err(data->dev, "Not support N driving for pin: %s\n", name);
431
+
dev_err(data->dev, "N driving unsupported for pin: %s\n", name);
497
432
return -ENOTSUPP;
498
433
}
499
434
set_val = arg;
···
510
445
case RTD_DUTY_CYCLE:
511
446
sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
512
447
if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) {
513
-
dev_err(data->dev, "Not support duty cycle for pin: %s\n", name);
448
+
dev_err(data->dev, "Duty cycle unsupported for pin: %s\n", name);
514
449
return -ENOTSUPP;
515
450
}
516
451
set_val = arg;
···
521
456
break;
522
457
523
458
default:
524
-
dev_err(data->dev, "unsupported pinconf: %d\n", (u32)param);
525
-
return -EINVAL;
459
+
dev_dbg(data->dev, "unsupported pinconf: %d\n", (u32)param);
460
+
return -ENOTSUPP;
526
461
}
527
462
528
463
ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val);
···
605
540
.use_relaxed_mmio = true,
606
541
};
607
542
543
+
static int rtd_pinctrl_init_pm(struct rtd_pinctrl *data)
544
+
{
545
+
const struct rtd_pin_range *pin_range = data->info->pin_range;
546
+
struct device *dev = data->pcdev->dev;
547
+
const struct rtd_reg_range *range;
548
+
size_t num_entries;
549
+
int i;
550
+
551
+
data->saved_regs = devm_kcalloc(dev, pin_range->num_ranges, sizeof(u32 *), GFP_KERNEL);
552
+
if (!data->saved_regs)
553
+
return -ENOMEM;
554
+
555
+
for (i = 0; i < pin_range->num_ranges; i++) {
556
+
range = &pin_range->ranges[i];
557
+
num_entries = range->len / 4;
558
+
559
+
data->saved_regs[i] = devm_kzalloc(dev, num_entries * sizeof(u32), GFP_KERNEL);
560
+
if (!data->saved_regs[i])
561
+
return -ENOMEM;
562
+
}
563
+
564
+
return 0;
565
+
}
566
+
608
567
int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc)
609
568
{
610
569
struct rtd_pinctrl *data;
611
-
int ret;
612
570
613
571
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
614
572
if (!data)
615
573
return -ENOMEM;
616
574
617
-
data->base = of_iomap(pdev->dev.of_node, 0);
618
-
if (!data->base)
619
-
return -ENOMEM;
575
+
data->base = devm_platform_ioremap_resource(pdev, 0);
576
+
if (IS_ERR(data->base))
577
+
return dev_err_probe(&pdev->dev, PTR_ERR(data->base),
578
+
"Failed to ioremap resource\n");
620
579
621
580
data->dev = &pdev->dev;
622
581
data->info = desc;
···
656
567
data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base,
657
568
&rtd_pinctrl_regmap_config);
658
569
659
-
if (IS_ERR(data->regmap_pinctrl)) {
660
-
dev_err(data->dev, "failed to init regmap: %ld\n",
661
-
PTR_ERR(data->regmap_pinctrl));
662
-
ret = PTR_ERR(data->regmap_pinctrl);
663
-
goto unmap;
664
-
}
570
+
if (IS_ERR(data->regmap_pinctrl))
571
+
return dev_err_probe(data->dev, PTR_ERR(data->regmap_pinctrl),
572
+
"Failed to init regmap\n");
665
573
666
-
data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data);
667
-
if (IS_ERR(data->pcdev)) {
668
-
ret = PTR_ERR(data->pcdev);
669
-
goto unmap;
670
-
}
574
+
data->pcdev = devm_pinctrl_register(&pdev->dev, &data->desc, data);
575
+
if (IS_ERR(data->pcdev))
576
+
return dev_err_probe(data->dev, PTR_ERR(data->pcdev),
577
+
"Failed to register pinctrl\n");
671
578
672
579
platform_set_drvdata(pdev, data);
673
580
674
581
dev_dbg(&pdev->dev, "probed\n");
675
582
676
-
return 0;
583
+
if (data->info->pin_range) {
584
+
if (rtd_pinctrl_init_pm(data))
585
+
return -ENOMEM;
586
+
}
677
587
678
-
unmap:
679
-
iounmap(data->base);
680
-
return ret;
588
+
return 0;
681
589
}
682
590
EXPORT_SYMBOL(rtd_pinctrl_probe);
683
591
592
+
static int realtek_pinctrl_suspend(struct device *dev)
593
+
{
594
+
struct rtd_pinctrl *data = dev_get_drvdata(dev);
595
+
const struct rtd_pin_range *pin_range = data->info->pin_range;
596
+
const struct rtd_reg_range *range;
597
+
u32 *range_regs;
598
+
int count;
599
+
int i, j;
600
+
int ret;
601
+
602
+
if (!data->saved_regs)
603
+
return 0;
604
+
605
+
for (i = 0; i < pin_range->num_ranges; i++) {
606
+
range = &pin_range->ranges[i];
607
+
range_regs = data->saved_regs[i];
608
+
count = range->len / 4;
609
+
610
+
for (j = 0; j < count; j++) {
611
+
ret = regmap_read(data->regmap_pinctrl, range->offset + (j * 4),
612
+
&range_regs[j]);
613
+
if (ret) {
614
+
dev_err(dev, "failed to store register 0x%x: %d\n",
615
+
range->offset + (j * 4), ret);
616
+
return ret;
617
+
}
618
+
}
619
+
}
620
+
621
+
return 0;
622
+
}
623
+
624
+
static int realtek_pinctrl_resume(struct device *dev)
625
+
{
626
+
struct rtd_pinctrl *data = dev_get_drvdata(dev);
627
+
const struct rtd_pin_range *pin_range = data->info->pin_range;
628
+
const struct rtd_reg_range *range;
629
+
u32 *range_regs;
630
+
int count;
631
+
int i, j;
632
+
int ret;
633
+
634
+
if (!data->saved_regs)
635
+
return 0;
636
+
637
+
for (i = 0; i < pin_range->num_ranges; i++) {
638
+
range = &pin_range->ranges[i];
639
+
range_regs = data->saved_regs[i];
640
+
count = range->len / 4;
641
+
642
+
for (j = 0; j < count; j++) {
643
+
ret = regmap_write(data->regmap_pinctrl, range->offset + (j * 4),
644
+
range_regs[j]);
645
+
if (ret) {
646
+
dev_err(dev, "failed to restore register 0x%x: %d\n",
647
+
range->offset + (j * 4), ret);
648
+
return ret;
649
+
}
650
+
}
651
+
}
652
+
return 0;
653
+
}
654
+
655
+
const struct dev_pm_ops realtek_pinctrl_pm_ops = {
656
+
NOIRQ_SYSTEM_SLEEP_PM_OPS(realtek_pinctrl_suspend, realtek_pinctrl_resume)
657
+
};
658
+
EXPORT_SYMBOL_GPL(realtek_pinctrl_pm_ops);
659
+
684
660
MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver");
685
-
MODULE_LICENSE("GPL v2");
661
+
MODULE_LICENSE("GPL");
+50
drivers/pinctrl/realtek/pinctrl-rtd.h
+50
drivers/pinctrl/realtek/pinctrl-rtd.h
···
34
34
unsigned int smt_offset;
35
35
unsigned int power_offset;
36
36
unsigned int curr_type;
37
+
unsigned int input_volt_offset;
38
+
unsigned int slew_rate_offset;
39
+
unsigned int hvil_offset;
37
40
};
38
41
39
42
struct rtd_pin_sconfig_desc {
···
48
45
unsigned int ndrive_maskbits;
49
46
unsigned int pdrive_offset;
50
47
unsigned int pdrive_maskbits;
48
+
};
49
+
50
+
struct rtd_reg_range {
51
+
unsigned int offset;
52
+
size_t len;
53
+
};
54
+
55
+
struct rtd_pin_range {
56
+
const struct rtd_reg_range *ranges;
57
+
const int num_ranges;
51
58
};
52
59
53
60
struct rtd_pin_desc {
···
98
85
.curr_type = _curr_type, \
99
86
}
100
87
88
+
#define RTK_PIN_CONFIG_V2(_name, _reg_off, _base_bit, _pud_en_off, \
89
+
_pud_sel_off, _curr_off, _smt_off, _pow_off, _input_volt_off, \
90
+
_curr_type) \
91
+
{ \
92
+
.name = # _name, \
93
+
.reg_offset = _reg_off, \
94
+
.base_bit = _base_bit, \
95
+
.pud_en_offset = _pud_en_off, \
96
+
.pud_sel_offset = _pud_sel_off, \
97
+
.curr_offset = _curr_off, \
98
+
.smt_offset = _smt_off, \
99
+
.power_offset = _pow_off, \
100
+
.input_volt_offset = _input_volt_off, \
101
+
.curr_type = _curr_type, \
102
+
}
103
+
104
+
#define RTK_PIN_CONFIG_I2C(_name, _reg_off, _base_bit, _pud_en_off, \
105
+
_pud_sel_off, _curr_off, _smt_off, _hvil_off, _sr_off, _pow_off, \
106
+
_input_volt_off, _curr_type) \
107
+
{ \
108
+
.name = # _name, \
109
+
.reg_offset = _reg_off, \
110
+
.base_bit = _base_bit, \
111
+
.pud_en_offset = _pud_en_off, \
112
+
.pud_sel_offset = _pud_sel_off, \
113
+
.curr_offset = _curr_off, \
114
+
.smt_offset = _smt_off, \
115
+
.hvil_offset = _hvil_off, \
116
+
.slew_rate_offset = _sr_off, \
117
+
.power_offset = _pow_off, \
118
+
.input_volt_offset = _input_volt_off, \
119
+
.curr_type = _curr_type, \
120
+
}
121
+
101
122
#define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \
102
123
_n_offset, _n_mask, _p_offset, _p_mask) \
103
124
{ \
···
166
119
unsigned int num_sconfigs;
167
120
struct rtd_pin_reg_list *lists;
168
121
unsigned int num_regs;
122
+
const struct rtd_pin_range *pin_range;
169
123
};
170
124
171
125
int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc);
126
+
127
+
extern const struct dev_pm_ops realtek_pinctrl_pm_ops;
+3138
drivers/pinctrl/realtek/pinctrl-rtd1625.c
+3138
drivers/pinctrl/realtek/pinctrl-rtd1625.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Realtek DHC 1625 pin controller driver
4
+
*
5
+
* Copyright (c) 2023 Realtek Semiconductor Corp.
6
+
*
7
+
*/
8
+
9
+
#include <linux/module.h>
10
+
#include <linux/of.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/pinctrl/pinctrl.h>
13
+
14
+
#include "pinctrl-rtd.h"
15
+
16
+
enum rtd1625_iso_pins_enum {
17
+
RTD1625_ISO_GPIO_8 = 0,
18
+
RTD1625_ISO_GPIO_9,
19
+
RTD1625_ISO_GPIO_10,
20
+
RTD1625_ISO_GPIO_11,
21
+
RTD1625_ISO_USB_CC1,
22
+
RTD1625_ISO_USB_CC2,
23
+
RTD1625_ISO_GPIO_45,
24
+
RTD1625_ISO_GPIO_46,
25
+
RTD1625_ISO_GPIO_47,
26
+
RTD1625_ISO_GPIO_48,
27
+
RTD1625_ISO_GPIO_49,
28
+
RTD1625_ISO_GPIO_50,
29
+
RTD1625_ISO_GPIO_52,
30
+
RTD1625_ISO_GPIO_94,
31
+
RTD1625_ISO_GPIO_95,
32
+
RTD1625_ISO_GPIO_96,
33
+
RTD1625_ISO_GPIO_97,
34
+
RTD1625_ISO_GPIO_98,
35
+
RTD1625_ISO_GPIO_99,
36
+
RTD1625_ISO_GPIO_100,
37
+
RTD1625_ISO_GPIO_101,
38
+
RTD1625_ISO_GPIO_102,
39
+
RTD1625_ISO_GPIO_103,
40
+
RTD1625_ISO_GPIO_104,
41
+
RTD1625_ISO_GPIO_105,
42
+
RTD1625_ISO_GPIO_106,
43
+
RTD1625_ISO_GPIO_107,
44
+
RTD1625_ISO_GPIO_108,
45
+
RTD1625_ISO_GPIO_109,
46
+
RTD1625_ISO_GPIO_110,
47
+
RTD1625_ISO_GPIO_111,
48
+
RTD1625_ISO_GPIO_112,
49
+
RTD1625_ISO_GPIO_128,
50
+
RTD1625_ISO_GPIO_129,
51
+
RTD1625_ISO_GPIO_130,
52
+
RTD1625_ISO_GPIO_131,
53
+
RTD1625_ISO_GPIO_145,
54
+
RTD1625_ISO_GPIO_146,
55
+
RTD1625_ISO_GPIO_147,
56
+
RTD1625_ISO_GPIO_148,
57
+
RTD1625_ISO_GPIO_149,
58
+
RTD1625_ISO_GPIO_150,
59
+
RTD1625_ISO_GPIO_151,
60
+
RTD1625_ISO_GPIO_152,
61
+
RTD1625_ISO_GPIO_153,
62
+
RTD1625_ISO_GPIO_154,
63
+
RTD1625_ISO_GPIO_155,
64
+
RTD1625_ISO_GPIO_156,
65
+
RTD1625_ISO_GPIO_157,
66
+
RTD1625_ISO_GPIO_158,
67
+
RTD1625_ISO_GPIO_159,
68
+
RTD1625_ISO_GPIO_160,
69
+
RTD1625_ISO_GPIO_161,
70
+
RTD1625_ISO_GPIO_162,
71
+
RTD1625_ISO_GPIO_163,
72
+
RTD1625_ISO_HI_WIDTH,
73
+
RTD1625_ISO_SF_EN,
74
+
RTD1625_ISO_ARM_TRACE_DBG_EN,
75
+
RTD1625_ISO_EJTAG_AUCPU0_LOC,
76
+
RTD1625_ISO_EJTAG_AUCPU1_LOC,
77
+
RTD1625_ISO_EJTAG_VE2_LOC,
78
+
RTD1625_ISO_EJTAG_SCPU_LOC,
79
+
RTD1625_ISO_EJTAG_PCPU_LOC,
80
+
RTD1625_ISO_EJTAG_ACPU_LOC,
81
+
RTD1625_ISO_I2C6_LOC,
82
+
RTD1625_ISO_UART0_LOC,
83
+
RTD1625_ISO_AI_I2S1_LOC,
84
+
RTD1625_ISO_AO_I2S1_LOC,
85
+
RTD1625_ISO_ETN_PHY_LOC,
86
+
RTD1625_ISO_SPDIF_LOC,
87
+
RTD1625_ISO_RGMII_VDSEL,
88
+
RTD1625_ISO_CSI_VDSEL,
89
+
RTD1625_ISO_SPDIF_IN_MODE,
90
+
};
91
+
92
+
static const struct pinctrl_pin_desc rtd1625_iso_pins[] = {
93
+
PINCTRL_PIN(RTD1625_ISO_GPIO_8, "gpio_8"),
94
+
PINCTRL_PIN(RTD1625_ISO_GPIO_9, "gpio_9"),
95
+
PINCTRL_PIN(RTD1625_ISO_GPIO_10, "gpio_10"),
96
+
PINCTRL_PIN(RTD1625_ISO_GPIO_11, "gpio_11"),
97
+
PINCTRL_PIN(RTD1625_ISO_USB_CC1, "usb_cc1"),
98
+
PINCTRL_PIN(RTD1625_ISO_USB_CC2, "usb_cc2"),
99
+
PINCTRL_PIN(RTD1625_ISO_GPIO_45, "gpio_45"),
100
+
PINCTRL_PIN(RTD1625_ISO_GPIO_46, "gpio_46"),
101
+
PINCTRL_PIN(RTD1625_ISO_GPIO_47, "gpio_47"),
102
+
PINCTRL_PIN(RTD1625_ISO_GPIO_48, "gpio_48"),
103
+
PINCTRL_PIN(RTD1625_ISO_GPIO_49, "gpio_49"),
104
+
PINCTRL_PIN(RTD1625_ISO_GPIO_50, "gpio_50"),
105
+
PINCTRL_PIN(RTD1625_ISO_GPIO_52, "gpio_52"),
106
+
PINCTRL_PIN(RTD1625_ISO_GPIO_94, "gpio_94"),
107
+
PINCTRL_PIN(RTD1625_ISO_GPIO_95, "gpio_95"),
108
+
PINCTRL_PIN(RTD1625_ISO_GPIO_96, "gpio_96"),
109
+
PINCTRL_PIN(RTD1625_ISO_GPIO_97, "gpio_97"),
110
+
PINCTRL_PIN(RTD1625_ISO_GPIO_98, "gpio_98"),
111
+
PINCTRL_PIN(RTD1625_ISO_GPIO_99, "gpio_99"),
112
+
PINCTRL_PIN(RTD1625_ISO_GPIO_100, "gpio_100"),
113
+
PINCTRL_PIN(RTD1625_ISO_GPIO_101, "gpio_101"),
114
+
PINCTRL_PIN(RTD1625_ISO_GPIO_102, "gpio_102"),
115
+
PINCTRL_PIN(RTD1625_ISO_GPIO_103, "gpio_103"),
116
+
PINCTRL_PIN(RTD1625_ISO_GPIO_104, "gpio_104"),
117
+
PINCTRL_PIN(RTD1625_ISO_GPIO_105, "gpio_105"),
118
+
PINCTRL_PIN(RTD1625_ISO_GPIO_106, "gpio_106"),
119
+
PINCTRL_PIN(RTD1625_ISO_GPIO_107, "gpio_107"),
120
+
PINCTRL_PIN(RTD1625_ISO_GPIO_108, "gpio_108"),
121
+
PINCTRL_PIN(RTD1625_ISO_GPIO_109, "gpio_109"),
122
+
PINCTRL_PIN(RTD1625_ISO_GPIO_110, "gpio_110"),
123
+
PINCTRL_PIN(RTD1625_ISO_GPIO_111, "gpio_111"),
124
+
PINCTRL_PIN(RTD1625_ISO_GPIO_112, "gpio_112"),
125
+
PINCTRL_PIN(RTD1625_ISO_GPIO_128, "gpio_128"),
126
+
PINCTRL_PIN(RTD1625_ISO_GPIO_129, "gpio_129"),
127
+
PINCTRL_PIN(RTD1625_ISO_GPIO_130, "gpio_130"),
128
+
PINCTRL_PIN(RTD1625_ISO_GPIO_131, "gpio_131"),
129
+
PINCTRL_PIN(RTD1625_ISO_GPIO_145, "gpio_145"),
130
+
PINCTRL_PIN(RTD1625_ISO_GPIO_146, "gpio_146"),
131
+
PINCTRL_PIN(RTD1625_ISO_GPIO_147, "gpio_147"),
132
+
PINCTRL_PIN(RTD1625_ISO_GPIO_148, "gpio_148"),
133
+
PINCTRL_PIN(RTD1625_ISO_GPIO_149, "gpio_149"),
134
+
PINCTRL_PIN(RTD1625_ISO_GPIO_150, "gpio_150"),
135
+
PINCTRL_PIN(RTD1625_ISO_GPIO_151, "gpio_151"),
136
+
PINCTRL_PIN(RTD1625_ISO_GPIO_152, "gpio_152"),
137
+
PINCTRL_PIN(RTD1625_ISO_GPIO_153, "gpio_153"),
138
+
PINCTRL_PIN(RTD1625_ISO_GPIO_154, "gpio_154"),
139
+
PINCTRL_PIN(RTD1625_ISO_GPIO_155, "gpio_155"),
140
+
PINCTRL_PIN(RTD1625_ISO_GPIO_156, "gpio_156"),
141
+
PINCTRL_PIN(RTD1625_ISO_GPIO_157, "gpio_157"),
142
+
PINCTRL_PIN(RTD1625_ISO_GPIO_158, "gpio_158"),
143
+
PINCTRL_PIN(RTD1625_ISO_GPIO_159, "gpio_159"),
144
+
PINCTRL_PIN(RTD1625_ISO_GPIO_160, "gpio_160"),
145
+
PINCTRL_PIN(RTD1625_ISO_GPIO_161, "gpio_161"),
146
+
PINCTRL_PIN(RTD1625_ISO_GPIO_162, "gpio_162"),
147
+
PINCTRL_PIN(RTD1625_ISO_GPIO_163, "gpio_163"),
148
+
PINCTRL_PIN(RTD1625_ISO_HI_WIDTH, "hi_width"),
149
+
PINCTRL_PIN(RTD1625_ISO_SF_EN, "sf_en"),
150
+
PINCTRL_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
151
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"),
152
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"),
153
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_VE2_LOC, "ejtag_ve2_loc"),
154
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
155
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, "ejtag_pcpu_loc"),
156
+
PINCTRL_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
157
+
PINCTRL_PIN(RTD1625_ISO_I2C6_LOC, "i2c6_loc"),
158
+
PINCTRL_PIN(RTD1625_ISO_UART0_LOC, "uart0_loc"),
159
+
PINCTRL_PIN(RTD1625_ISO_AI_I2S1_LOC, "ai_i2s1_loc"),
160
+
PINCTRL_PIN(RTD1625_ISO_AO_I2S1_LOC, "ao_i2s1_loc"),
161
+
PINCTRL_PIN(RTD1625_ISO_ETN_PHY_LOC, "etn_phy_loc"),
162
+
PINCTRL_PIN(RTD1625_ISO_SPDIF_LOC, "spdif_loc"),
163
+
PINCTRL_PIN(RTD1625_ISO_RGMII_VDSEL, "rgmii_vdsel"),
164
+
PINCTRL_PIN(RTD1625_ISO_CSI_VDSEL, "csi_vdsel"),
165
+
PINCTRL_PIN(RTD1625_ISO_SPDIF_IN_MODE, "spdif_in_mode"),
166
+
};
167
+
168
+
enum rtd1625_isom_pins_enum {
169
+
RTD1625_ISOM_GPIO_0 = 0,
170
+
RTD1625_ISOM_GPIO_1,
171
+
RTD1625_ISOM_GPIO_28,
172
+
RTD1625_ISOM_GPIO_29,
173
+
RTD1625_ISOM_IR_RX_LOC,
174
+
};
175
+
176
+
static const struct pinctrl_pin_desc rtd1625_isom_pins[] = {
177
+
PINCTRL_PIN(RTD1625_ISOM_GPIO_0, "gpio_0"),
178
+
PINCTRL_PIN(RTD1625_ISOM_GPIO_1, "gpio_1"),
179
+
PINCTRL_PIN(RTD1625_ISOM_GPIO_28, "gpio_28"),
180
+
PINCTRL_PIN(RTD1625_ISOM_GPIO_29, "gpio_29"),
181
+
PINCTRL_PIN(RTD1625_ISOM_IR_RX_LOC, "ir_rx_loc"),
182
+
};
183
+
184
+
enum rtd1625_ve4_pins_enum {
185
+
RTD1625_VE4_GPIO_2 = 0,
186
+
RTD1625_VE4_GPIO_3,
187
+
RTD1625_VE4_GPIO_4,
188
+
RTD1625_VE4_GPIO_5,
189
+
RTD1625_VE4_GPIO_6,
190
+
RTD1625_VE4_GPIO_7,
191
+
RTD1625_VE4_GPIO_12,
192
+
RTD1625_VE4_GPIO_13,
193
+
RTD1625_VE4_GPIO_16,
194
+
RTD1625_VE4_GPIO_17,
195
+
RTD1625_VE4_GPIO_18,
196
+
RTD1625_VE4_GPIO_19,
197
+
RTD1625_VE4_GPIO_23,
198
+
RTD1625_VE4_GPIO_24,
199
+
RTD1625_VE4_GPIO_25,
200
+
RTD1625_VE4_GPIO_30,
201
+
RTD1625_VE4_GPIO_31,
202
+
RTD1625_VE4_GPIO_32,
203
+
RTD1625_VE4_GPIO_33,
204
+
RTD1625_VE4_GPIO_34,
205
+
RTD1625_VE4_GPIO_35,
206
+
RTD1625_VE4_GPIO_42,
207
+
RTD1625_VE4_GPIO_43,
208
+
RTD1625_VE4_GPIO_44,
209
+
RTD1625_VE4_GPIO_51,
210
+
RTD1625_VE4_GPIO_53,
211
+
RTD1625_VE4_GPIO_54,
212
+
RTD1625_VE4_GPIO_55,
213
+
RTD1625_VE4_GPIO_56,
214
+
RTD1625_VE4_GPIO_57,
215
+
RTD1625_VE4_GPIO_58,
216
+
RTD1625_VE4_GPIO_59,
217
+
RTD1625_VE4_GPIO_60,
218
+
RTD1625_VE4_GPIO_61,
219
+
RTD1625_VE4_GPIO_62,
220
+
RTD1625_VE4_GPIO_63,
221
+
RTD1625_VE4_GPIO_92,
222
+
RTD1625_VE4_GPIO_93,
223
+
RTD1625_VE4_GPIO_132,
224
+
RTD1625_VE4_GPIO_133,
225
+
RTD1625_VE4_GPIO_134,
226
+
RTD1625_VE4_GPIO_135,
227
+
RTD1625_VE4_GPIO_136,
228
+
RTD1625_VE4_GPIO_137,
229
+
RTD1625_VE4_GPIO_138,
230
+
RTD1625_VE4_GPIO_139,
231
+
RTD1625_VE4_GPIO_140,
232
+
RTD1625_VE4_GPIO_141,
233
+
RTD1625_VE4_GPIO_142,
234
+
RTD1625_VE4_GPIO_143,
235
+
RTD1625_VE4_GPIO_144,
236
+
RTD1625_VE4_GPIO_164,
237
+
RTD1625_VE4_GPIO_165,
238
+
RTD1625_VE4_UART_LOC,
239
+
};
240
+
241
+
static const struct pinctrl_pin_desc rtd1625_ve4_pins[] = {
242
+
PINCTRL_PIN(RTD1625_VE4_GPIO_2, "gpio_2"),
243
+
PINCTRL_PIN(RTD1625_VE4_GPIO_3, "gpio_3"),
244
+
PINCTRL_PIN(RTD1625_VE4_GPIO_4, "gpio_4"),
245
+
PINCTRL_PIN(RTD1625_VE4_GPIO_5, "gpio_5"),
246
+
PINCTRL_PIN(RTD1625_VE4_GPIO_6, "gpio_6"),
247
+
PINCTRL_PIN(RTD1625_VE4_GPIO_7, "gpio_7"),
248
+
PINCTRL_PIN(RTD1625_VE4_GPIO_12, "gpio_12"),
249
+
PINCTRL_PIN(RTD1625_VE4_GPIO_13, "gpio_13"),
250
+
PINCTRL_PIN(RTD1625_VE4_GPIO_16, "gpio_16"),
251
+
PINCTRL_PIN(RTD1625_VE4_GPIO_17, "gpio_17"),
252
+
PINCTRL_PIN(RTD1625_VE4_GPIO_18, "gpio_18"),
253
+
PINCTRL_PIN(RTD1625_VE4_GPIO_19, "gpio_19"),
254
+
PINCTRL_PIN(RTD1625_VE4_GPIO_23, "gpio_23"),
255
+
PINCTRL_PIN(RTD1625_VE4_GPIO_24, "gpio_24"),
256
+
PINCTRL_PIN(RTD1625_VE4_GPIO_25, "gpio_25"),
257
+
PINCTRL_PIN(RTD1625_VE4_GPIO_30, "gpio_30"),
258
+
PINCTRL_PIN(RTD1625_VE4_GPIO_31, "gpio_31"),
259
+
PINCTRL_PIN(RTD1625_VE4_GPIO_32, "gpio_32"),
260
+
PINCTRL_PIN(RTD1625_VE4_GPIO_33, "gpio_33"),
261
+
PINCTRL_PIN(RTD1625_VE4_GPIO_34, "gpio_34"),
262
+
PINCTRL_PIN(RTD1625_VE4_GPIO_35, "gpio_35"),
263
+
PINCTRL_PIN(RTD1625_VE4_GPIO_42, "gpio_42"),
264
+
PINCTRL_PIN(RTD1625_VE4_GPIO_43, "gpio_43"),
265
+
PINCTRL_PIN(RTD1625_VE4_GPIO_44, "gpio_44"),
266
+
PINCTRL_PIN(RTD1625_VE4_GPIO_51, "gpio_51"),
267
+
PINCTRL_PIN(RTD1625_VE4_GPIO_53, "gpio_53"),
268
+
PINCTRL_PIN(RTD1625_VE4_GPIO_54, "gpio_54"),
269
+
PINCTRL_PIN(RTD1625_VE4_GPIO_55, "gpio_55"),
270
+
PINCTRL_PIN(RTD1625_VE4_GPIO_56, "gpio_56"),
271
+
PINCTRL_PIN(RTD1625_VE4_GPIO_57, "gpio_57"),
272
+
PINCTRL_PIN(RTD1625_VE4_GPIO_58, "gpio_58"),
273
+
PINCTRL_PIN(RTD1625_VE4_GPIO_59, "gpio_59"),
274
+
PINCTRL_PIN(RTD1625_VE4_GPIO_60, "gpio_60"),
275
+
PINCTRL_PIN(RTD1625_VE4_GPIO_61, "gpio_61"),
276
+
PINCTRL_PIN(RTD1625_VE4_GPIO_62, "gpio_62"),
277
+
PINCTRL_PIN(RTD1625_VE4_GPIO_63, "gpio_63"),
278
+
PINCTRL_PIN(RTD1625_VE4_GPIO_92, "gpio_92"),
279
+
PINCTRL_PIN(RTD1625_VE4_GPIO_93, "gpio_93"),
280
+
PINCTRL_PIN(RTD1625_VE4_GPIO_132, "gpio_132"),
281
+
PINCTRL_PIN(RTD1625_VE4_GPIO_133, "gpio_133"),
282
+
PINCTRL_PIN(RTD1625_VE4_GPIO_134, "gpio_134"),
283
+
PINCTRL_PIN(RTD1625_VE4_GPIO_135, "gpio_135"),
284
+
PINCTRL_PIN(RTD1625_VE4_GPIO_136, "gpio_136"),
285
+
PINCTRL_PIN(RTD1625_VE4_GPIO_137, "gpio_137"),
286
+
PINCTRL_PIN(RTD1625_VE4_GPIO_138, "gpio_138"),
287
+
PINCTRL_PIN(RTD1625_VE4_GPIO_139, "gpio_139"),
288
+
PINCTRL_PIN(RTD1625_VE4_GPIO_140, "gpio_140"),
289
+
PINCTRL_PIN(RTD1625_VE4_GPIO_141, "gpio_141"),
290
+
PINCTRL_PIN(RTD1625_VE4_GPIO_142, "gpio_142"),
291
+
PINCTRL_PIN(RTD1625_VE4_GPIO_143, "gpio_143"),
292
+
PINCTRL_PIN(RTD1625_VE4_GPIO_144, "gpio_144"),
293
+
PINCTRL_PIN(RTD1625_VE4_GPIO_164, "gpio_164"),
294
+
PINCTRL_PIN(RTD1625_VE4_GPIO_165, "gpio_165"),
295
+
PINCTRL_PIN(RTD1625_VE4_UART_LOC, "ve4_uart_loc"),
296
+
};
297
+
298
+
enum rtd1625_main2_pins_enum {
299
+
RTD1625_MAIN2_GPIO_14 = 0,
300
+
RTD1625_MAIN2_GPIO_15,
301
+
RTD1625_MAIN2_GPIO_20,
302
+
RTD1625_MAIN2_GPIO_21,
303
+
RTD1625_MAIN2_GPIO_22,
304
+
RTD1625_MAIN2_HIF_DATA,
305
+
RTD1625_MAIN2_HIF_EN,
306
+
RTD1625_MAIN2_HIF_RDY,
307
+
RTD1625_MAIN2_HIF_CLK,
308
+
RTD1625_MAIN2_GPIO_40,
309
+
RTD1625_MAIN2_GPIO_41,
310
+
RTD1625_MAIN2_GPIO_64,
311
+
RTD1625_MAIN2_GPIO_65,
312
+
RTD1625_MAIN2_GPIO_66,
313
+
RTD1625_MAIN2_GPIO_67,
314
+
RTD1625_MAIN2_EMMC_DATA_0,
315
+
RTD1625_MAIN2_EMMC_DATA_1,
316
+
RTD1625_MAIN2_EMMC_DATA_2,
317
+
RTD1625_MAIN2_EMMC_DATA_3,
318
+
RTD1625_MAIN2_EMMC_DATA_4,
319
+
RTD1625_MAIN2_EMMC_DATA_5,
320
+
RTD1625_MAIN2_EMMC_DATA_6,
321
+
RTD1625_MAIN2_EMMC_DATA_7,
322
+
RTD1625_MAIN2_EMMC_RST_N,
323
+
RTD1625_MAIN2_EMMC_CMD,
324
+
RTD1625_MAIN2_EMMC_CLK,
325
+
RTD1625_MAIN2_EMMC_DD_SB,
326
+
RTD1625_MAIN2_GPIO_80,
327
+
RTD1625_MAIN2_GPIO_81,
328
+
RTD1625_MAIN2_GPIO_82,
329
+
RTD1625_MAIN2_GPIO_83,
330
+
RTD1625_MAIN2_GPIO_84,
331
+
RTD1625_MAIN2_GPIO_85,
332
+
RTD1625_MAIN2_GPIO_86,
333
+
RTD1625_MAIN2_GPIO_87,
334
+
RTD1625_MAIN2_GPIO_88,
335
+
RTD1625_MAIN2_GPIO_89,
336
+
RTD1625_MAIN2_GPIO_90,
337
+
RTD1625_MAIN2_GPIO_91,
338
+
};
339
+
340
+
static const struct pinctrl_pin_desc rtd1625_main2_pins[] = {
341
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_14, "gpio_14"),
342
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_15, "gpio_15"),
343
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_20, "gpio_20"),
344
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_21, "gpio_21"),
345
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_22, "gpio_22"),
346
+
PINCTRL_PIN(RTD1625_MAIN2_HIF_DATA, "hif_data"),
347
+
PINCTRL_PIN(RTD1625_MAIN2_HIF_EN, "hif_en"),
348
+
PINCTRL_PIN(RTD1625_MAIN2_HIF_RDY, "hif_rdy"),
349
+
PINCTRL_PIN(RTD1625_MAIN2_HIF_CLK, "hif_clk"),
350
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_40, "gpio_40"),
351
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_41, "gpio_41"),
352
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_64, "gpio_64"),
353
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_65, "gpio_65"),
354
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_66, "gpio_66"),
355
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_67, "gpio_67"),
356
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_0, "emmc_data_0"),
357
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_1, "emmc_data_1"),
358
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_2, "emmc_data_2"),
359
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_3, "emmc_data_3"),
360
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_4, "emmc_data_4"),
361
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_5, "emmc_data_5"),
362
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_6, "emmc_data_6"),
363
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_7, "emmc_data_7"),
364
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_RST_N, "emmc_rst_n"),
365
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_CMD, "emmc_cmd"),
366
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_CLK, "emmc_clk"),
367
+
PINCTRL_PIN(RTD1625_MAIN2_EMMC_DD_SB, "emmc_dd_sb"),
368
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_80, "gpio_80"),
369
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_81, "gpio_81"),
370
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_82, "gpio_82"),
371
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_83, "gpio_83"),
372
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_84, "gpio_84"),
373
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_85, "gpio_85"),
374
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_86, "gpio_86"),
375
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_87, "gpio_87"),
376
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_88, "gpio_88"),
377
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_89, "gpio_89"),
378
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_90, "gpio_90"),
379
+
PINCTRL_PIN(RTD1625_MAIN2_GPIO_91, "gpio_91"),
380
+
};
381
+
382
+
#define DECLARE_RTD1625_PIN(_pin, _name) \
383
+
static const unsigned int rtd1625_##_name##_pins[] = { _pin }
384
+
385
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_8, gpio_8);
386
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_9, gpio_9);
387
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_10, gpio_10);
388
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_11, gpio_11);
389
+
DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC1, usb_cc1);
390
+
DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC2, usb_cc2);
391
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_45, gpio_45);
392
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_46, gpio_46);
393
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_47, gpio_47);
394
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_48, gpio_48);
395
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_49, gpio_49);
396
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_50, gpio_50);
397
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_52, gpio_52);
398
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_94, gpio_94);
399
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_95, gpio_95);
400
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_96, gpio_96);
401
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_97, gpio_97);
402
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_98, gpio_98);
403
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_99, gpio_99);
404
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_100, gpio_100);
405
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_101, gpio_101);
406
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_102, gpio_102);
407
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_103, gpio_103);
408
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_104, gpio_104);
409
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_105, gpio_105);
410
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_106, gpio_106);
411
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_107, gpio_107);
412
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_108, gpio_108);
413
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_109, gpio_109);
414
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_110, gpio_110);
415
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_111, gpio_111);
416
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_112, gpio_112);
417
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_128, gpio_128);
418
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_129, gpio_129);
419
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_130, gpio_130);
420
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_131, gpio_131);
421
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_145, gpio_145);
422
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_146, gpio_146);
423
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_147, gpio_147);
424
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_148, gpio_148);
425
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_149, gpio_149);
426
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_150, gpio_150);
427
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_151, gpio_151);
428
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_152, gpio_152);
429
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_153, gpio_153);
430
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_154, gpio_154);
431
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_155, gpio_155);
432
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_156, gpio_156);
433
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_157, gpio_157);
434
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_158, gpio_158);
435
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_159, gpio_159);
436
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_160, gpio_160);
437
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_161, gpio_161);
438
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_162, gpio_162);
439
+
DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_163, gpio_163);
440
+
441
+
DECLARE_RTD1625_PIN(RTD1625_ISO_HI_WIDTH, hi_width);
442
+
DECLARE_RTD1625_PIN(RTD1625_ISO_SF_EN, sf_en);
443
+
DECLARE_RTD1625_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
444
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc);
445
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc);
446
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_VE2_LOC, ejtag_ve2_loc);
447
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
448
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, ejtag_pcpu_loc);
449
+
DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
450
+
451
+
DECLARE_RTD1625_PIN(RTD1625_ISO_I2C6_LOC, i2c6_loc);
452
+
DECLARE_RTD1625_PIN(RTD1625_ISO_UART0_LOC, uart0_loc);
453
+
DECLARE_RTD1625_PIN(RTD1625_ISO_AI_I2S1_LOC, ai_i2s1_loc);
454
+
DECLARE_RTD1625_PIN(RTD1625_ISO_AO_I2S1_LOC, ao_i2s1_loc);
455
+
DECLARE_RTD1625_PIN(RTD1625_ISO_ETN_PHY_LOC, etn_phy_loc);
456
+
DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_LOC, spdif_loc);
457
+
DECLARE_RTD1625_PIN(RTD1625_ISO_RGMII_VDSEL, rgmii_vdsel);
458
+
DECLARE_RTD1625_PIN(RTD1625_ISO_CSI_VDSEL, csi_vdsel);
459
+
DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_IN_MODE, spdif_in_mode);
460
+
461
+
DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_0, gpio_0);
462
+
DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_1, gpio_1);
463
+
DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_28, gpio_28);
464
+
DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_29, gpio_29);
465
+
DECLARE_RTD1625_PIN(RTD1625_ISOM_IR_RX_LOC, ir_rx_loc);
466
+
467
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_2, gpio_2);
468
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_3, gpio_3);
469
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_4, gpio_4);
470
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_5, gpio_5);
471
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_6, gpio_6);
472
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_7, gpio_7);
473
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_12, gpio_12);
474
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_13, gpio_13);
475
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_16, gpio_16);
476
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_17, gpio_17);
477
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_18, gpio_18);
478
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_19, gpio_19);
479
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_23, gpio_23);
480
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_24, gpio_24);
481
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_25, gpio_25);
482
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_30, gpio_30);
483
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_31, gpio_31);
484
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_32, gpio_32);
485
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_33, gpio_33);
486
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_34, gpio_34);
487
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_35, gpio_35);
488
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_42, gpio_42);
489
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_43, gpio_43);
490
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_44, gpio_44);
491
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_51, gpio_51);
492
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_53, gpio_53);
493
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_54, gpio_54);
494
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_55, gpio_55);
495
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_56, gpio_56);
496
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_57, gpio_57);
497
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_58, gpio_58);
498
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_59, gpio_59);
499
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_60, gpio_60);
500
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_61, gpio_61);
501
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_62, gpio_62);
502
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_63, gpio_63);
503
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_92, gpio_92);
504
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_93, gpio_93);
505
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_132, gpio_132);
506
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_133, gpio_133);
507
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_134, gpio_134);
508
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_135, gpio_135);
509
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_136, gpio_136);
510
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_137, gpio_137);
511
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_138, gpio_138);
512
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_139, gpio_139);
513
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_140, gpio_140);
514
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_141, gpio_141);
515
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_142, gpio_142);
516
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_143, gpio_143);
517
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_144, gpio_144);
518
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_164, gpio_164);
519
+
DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_165, gpio_165);
520
+
DECLARE_RTD1625_PIN(RTD1625_VE4_UART_LOC, ve4_uart_loc);
521
+
522
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_RST_N, emmc_rst_n);
523
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DD_SB, emmc_dd_sb);
524
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CLK, emmc_clk);
525
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CMD, emmc_cmd);
526
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_0, emmc_data_0);
527
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_1, emmc_data_1);
528
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_2, emmc_data_2);
529
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_3, emmc_data_3);
530
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_4, emmc_data_4);
531
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_5, emmc_data_5);
532
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_6, emmc_data_6);
533
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_7, emmc_data_7);
534
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_14, gpio_14);
535
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_15, gpio_15);
536
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_20, gpio_20);
537
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_21, gpio_21);
538
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_22, gpio_22);
539
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_DATA, hif_data);
540
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_EN, hif_en);
541
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_RDY, hif_rdy);
542
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_CLK, hif_clk);
543
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_40, gpio_40);
544
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_41, gpio_41);
545
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_64, gpio_64);
546
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_65, gpio_65);
547
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_66, gpio_66);
548
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_67, gpio_67);
549
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_80, gpio_80);
550
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_81, gpio_81);
551
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_82, gpio_82);
552
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_83, gpio_83);
553
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_84, gpio_84);
554
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_85, gpio_85);
555
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_86, gpio_86);
556
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_87, gpio_87);
557
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_88, gpio_88);
558
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_89, gpio_89);
559
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_90, gpio_90);
560
+
DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_91, gpio_91);
561
+
562
+
#define RTD1625_GROUP(_name) \
563
+
{ \
564
+
.name = # _name, \
565
+
.pins = rtd1625_ ## _name ## _pins, \
566
+
.num_pins = ARRAY_SIZE(rtd1625_ ## _name ## _pins), \
567
+
}
568
+
569
+
static const struct rtd_pin_group_desc rtd1625_iso_pin_groups[] = {
570
+
RTD1625_GROUP(gpio_8),
571
+
RTD1625_GROUP(gpio_9),
572
+
RTD1625_GROUP(gpio_10),
573
+
RTD1625_GROUP(gpio_11),
574
+
RTD1625_GROUP(usb_cc1),
575
+
RTD1625_GROUP(usb_cc2),
576
+
RTD1625_GROUP(gpio_45),
577
+
RTD1625_GROUP(gpio_46),
578
+
RTD1625_GROUP(gpio_47),
579
+
RTD1625_GROUP(gpio_48),
580
+
RTD1625_GROUP(gpio_49),
581
+
RTD1625_GROUP(gpio_50),
582
+
RTD1625_GROUP(gpio_52),
583
+
RTD1625_GROUP(gpio_94),
584
+
RTD1625_GROUP(gpio_95),
585
+
RTD1625_GROUP(gpio_96),
586
+
RTD1625_GROUP(gpio_97),
587
+
RTD1625_GROUP(gpio_98),
588
+
RTD1625_GROUP(gpio_99),
589
+
RTD1625_GROUP(gpio_100),
590
+
RTD1625_GROUP(gpio_101),
591
+
RTD1625_GROUP(gpio_102),
592
+
RTD1625_GROUP(gpio_103),
593
+
RTD1625_GROUP(gpio_104),
594
+
RTD1625_GROUP(gpio_105),
595
+
RTD1625_GROUP(gpio_106),
596
+
RTD1625_GROUP(gpio_107),
597
+
RTD1625_GROUP(gpio_108),
598
+
RTD1625_GROUP(gpio_109),
599
+
RTD1625_GROUP(gpio_110),
600
+
RTD1625_GROUP(gpio_111),
601
+
RTD1625_GROUP(gpio_112),
602
+
RTD1625_GROUP(gpio_128),
603
+
RTD1625_GROUP(gpio_129),
604
+
RTD1625_GROUP(gpio_130),
605
+
RTD1625_GROUP(gpio_131),
606
+
RTD1625_GROUP(gpio_145),
607
+
RTD1625_GROUP(gpio_146),
608
+
RTD1625_GROUP(gpio_147),
609
+
RTD1625_GROUP(gpio_148),
610
+
RTD1625_GROUP(gpio_149),
611
+
RTD1625_GROUP(gpio_150),
612
+
RTD1625_GROUP(gpio_151),
613
+
RTD1625_GROUP(gpio_152),
614
+
RTD1625_GROUP(gpio_153),
615
+
RTD1625_GROUP(gpio_154),
616
+
RTD1625_GROUP(gpio_155),
617
+
RTD1625_GROUP(gpio_156),
618
+
RTD1625_GROUP(gpio_157),
619
+
RTD1625_GROUP(gpio_158),
620
+
RTD1625_GROUP(gpio_159),
621
+
RTD1625_GROUP(gpio_160),
622
+
RTD1625_GROUP(gpio_161),
623
+
RTD1625_GROUP(gpio_162),
624
+
RTD1625_GROUP(gpio_163),
625
+
RTD1625_GROUP(hi_width),
626
+
RTD1625_GROUP(sf_en),
627
+
RTD1625_GROUP(arm_trace_dbg_en),
628
+
RTD1625_GROUP(ejtag_aucpu0_loc),
629
+
RTD1625_GROUP(ejtag_aucpu1_loc),
630
+
RTD1625_GROUP(ejtag_ve2_loc),
631
+
RTD1625_GROUP(ejtag_scpu_loc),
632
+
RTD1625_GROUP(ejtag_pcpu_loc),
633
+
RTD1625_GROUP(ejtag_acpu_loc),
634
+
RTD1625_GROUP(i2c6_loc),
635
+
RTD1625_GROUP(uart0_loc),
636
+
RTD1625_GROUP(ai_i2s1_loc),
637
+
RTD1625_GROUP(ao_i2s1_loc),
638
+
RTD1625_GROUP(etn_phy_loc),
639
+
RTD1625_GROUP(spdif_loc),
640
+
RTD1625_GROUP(rgmii_vdsel),
641
+
RTD1625_GROUP(csi_vdsel),
642
+
RTD1625_GROUP(spdif_in_mode),
643
+
};
644
+
645
+
static const struct rtd_pin_group_desc rtd1625_isom_pin_groups[] = {
646
+
RTD1625_GROUP(gpio_0),
647
+
RTD1625_GROUP(gpio_1),
648
+
RTD1625_GROUP(gpio_28),
649
+
RTD1625_GROUP(gpio_29),
650
+
RTD1625_GROUP(ir_rx_loc),
651
+
};
652
+
653
+
static const struct rtd_pin_group_desc rtd1625_ve4_pin_groups[] = {
654
+
RTD1625_GROUP(gpio_2),
655
+
RTD1625_GROUP(gpio_3),
656
+
RTD1625_GROUP(gpio_4),
657
+
RTD1625_GROUP(gpio_5),
658
+
RTD1625_GROUP(gpio_6),
659
+
RTD1625_GROUP(gpio_7),
660
+
RTD1625_GROUP(gpio_12),
661
+
RTD1625_GROUP(gpio_13),
662
+
RTD1625_GROUP(gpio_16),
663
+
RTD1625_GROUP(gpio_17),
664
+
RTD1625_GROUP(gpio_18),
665
+
RTD1625_GROUP(gpio_19),
666
+
RTD1625_GROUP(gpio_23),
667
+
RTD1625_GROUP(gpio_24),
668
+
RTD1625_GROUP(gpio_25),
669
+
RTD1625_GROUP(gpio_30),
670
+
RTD1625_GROUP(gpio_31),
671
+
RTD1625_GROUP(gpio_32),
672
+
RTD1625_GROUP(gpio_33),
673
+
RTD1625_GROUP(gpio_34),
674
+
RTD1625_GROUP(gpio_35),
675
+
RTD1625_GROUP(gpio_42),
676
+
RTD1625_GROUP(gpio_43),
677
+
RTD1625_GROUP(gpio_44),
678
+
RTD1625_GROUP(gpio_51),
679
+
RTD1625_GROUP(gpio_53),
680
+
RTD1625_GROUP(gpio_54),
681
+
RTD1625_GROUP(gpio_55),
682
+
RTD1625_GROUP(gpio_56),
683
+
RTD1625_GROUP(gpio_57),
684
+
RTD1625_GROUP(gpio_58),
685
+
RTD1625_GROUP(gpio_59),
686
+
RTD1625_GROUP(gpio_60),
687
+
RTD1625_GROUP(gpio_61),
688
+
RTD1625_GROUP(gpio_62),
689
+
RTD1625_GROUP(gpio_63),
690
+
RTD1625_GROUP(gpio_92),
691
+
RTD1625_GROUP(gpio_93),
692
+
RTD1625_GROUP(gpio_132),
693
+
RTD1625_GROUP(gpio_133),
694
+
RTD1625_GROUP(gpio_134),
695
+
RTD1625_GROUP(gpio_135),
696
+
RTD1625_GROUP(gpio_136),
697
+
RTD1625_GROUP(gpio_137),
698
+
RTD1625_GROUP(gpio_138),
699
+
RTD1625_GROUP(gpio_139),
700
+
RTD1625_GROUP(gpio_140),
701
+
RTD1625_GROUP(gpio_141),
702
+
RTD1625_GROUP(gpio_142),
703
+
RTD1625_GROUP(gpio_143),
704
+
RTD1625_GROUP(gpio_144),
705
+
RTD1625_GROUP(gpio_164),
706
+
RTD1625_GROUP(gpio_165),
707
+
RTD1625_GROUP(ve4_uart_loc),
708
+
};
709
+
710
+
static const struct rtd_pin_group_desc rtd1625_main2_pin_groups[] = {
711
+
RTD1625_GROUP(gpio_14),
712
+
RTD1625_GROUP(gpio_15),
713
+
RTD1625_GROUP(gpio_20),
714
+
RTD1625_GROUP(gpio_21),
715
+
RTD1625_GROUP(gpio_22),
716
+
RTD1625_GROUP(hif_data),
717
+
RTD1625_GROUP(hif_en),
718
+
RTD1625_GROUP(hif_rdy),
719
+
RTD1625_GROUP(hif_clk),
720
+
RTD1625_GROUP(gpio_40),
721
+
RTD1625_GROUP(gpio_41),
722
+
RTD1625_GROUP(gpio_64),
723
+
RTD1625_GROUP(gpio_65),
724
+
RTD1625_GROUP(gpio_66),
725
+
RTD1625_GROUP(gpio_67),
726
+
RTD1625_GROUP(emmc_data_0),
727
+
RTD1625_GROUP(emmc_data_1),
728
+
RTD1625_GROUP(emmc_data_2),
729
+
RTD1625_GROUP(emmc_data_3),
730
+
RTD1625_GROUP(emmc_data_4),
731
+
RTD1625_GROUP(emmc_data_5),
732
+
RTD1625_GROUP(emmc_data_6),
733
+
RTD1625_GROUP(emmc_data_7),
734
+
RTD1625_GROUP(emmc_rst_n),
735
+
RTD1625_GROUP(emmc_cmd),
736
+
RTD1625_GROUP(emmc_clk),
737
+
RTD1625_GROUP(emmc_dd_sb),
738
+
RTD1625_GROUP(gpio_80),
739
+
RTD1625_GROUP(gpio_81),
740
+
RTD1625_GROUP(gpio_82),
741
+
RTD1625_GROUP(gpio_83),
742
+
RTD1625_GROUP(gpio_84),
743
+
RTD1625_GROUP(gpio_85),
744
+
RTD1625_GROUP(gpio_86),
745
+
RTD1625_GROUP(gpio_87),
746
+
RTD1625_GROUP(gpio_88),
747
+
RTD1625_GROUP(gpio_89),
748
+
RTD1625_GROUP(gpio_90),
749
+
RTD1625_GROUP(gpio_91),
750
+
};
751
+
752
+
static const char * const rtd1625_iso_gpio_groups[] = {
753
+
"gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104",
754
+
"gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11",
755
+
"gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130",
756
+
"gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149",
757
+
"gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155",
758
+
"gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161",
759
+
"gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48",
760
+
"gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95",
761
+
"gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2"
762
+
};
763
+
764
+
static const char * const rtd1625_iso_uart1_groups[] = {
765
+
"gpio_10", "gpio_11", "gpio_8", "gpio_9"
766
+
};
767
+
768
+
static const char * const rtd1625_iso_iso_tristate_groups[] = {
769
+
"gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104",
770
+
"gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11",
771
+
"gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130",
772
+
"gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149",
773
+
"gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155",
774
+
"gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161",
775
+
"gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48",
776
+
"gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95",
777
+
"gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2"
778
+
};
779
+
780
+
static const char * const rtd1625_iso_usb_cc1_groups[] = {
781
+
"usb_cc1"
782
+
};
783
+
784
+
static const char * const rtd1625_iso_usb_cc2_groups[] = {
785
+
"usb_cc2"
786
+
};
787
+
788
+
static const char * const rtd1625_iso_sdio_groups[] = {
789
+
"gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50"
790
+
};
791
+
792
+
static const char * const rtd1625_iso_scpu_ejtag_loc2_groups[] = {
793
+
"ejtag_scpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
794
+
};
795
+
796
+
static const char * const rtd1625_iso_acpu_ejtag_loc2_groups[] = {
797
+
"ejtag_acpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
798
+
};
799
+
800
+
static const char * const rtd1625_iso_pcpu_ejtag_loc2_groups[] = {
801
+
"ejtag_pcpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
802
+
};
803
+
804
+
static const char * const rtd1625_iso_aucpu0_ejtag_loc2_groups[] = {
805
+
"ejtag_aucpu0_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
806
+
};
807
+
808
+
static const char * const rtd1625_iso_ve2_ejtag_loc2_groups[] = {
809
+
"ejtag_ve2_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
810
+
};
811
+
812
+
static const char * const rtd1625_iso_aucpu1_ejtag_loc2_groups[] = {
813
+
"ejtag_aucpu1_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
814
+
};
815
+
816
+
static const char * const rtd1625_iso_pwm4_groups[] = {
817
+
"gpio_52"
818
+
};
819
+
820
+
static const char * const rtd1625_iso_uart7_groups[] = {
821
+
"gpio_94", "gpio_95"
822
+
};
823
+
824
+
static const char * const rtd1625_iso_pwm2_loc1_groups[] = {
825
+
"gpio_95"
826
+
};
827
+
828
+
static const char * const rtd1625_iso_uart8_groups[] = {
829
+
"gpio_96", "gpio_97"
830
+
};
831
+
832
+
static const char * const rtd1625_iso_pwm3_loc1_groups[] = {
833
+
"gpio_97"
834
+
};
835
+
836
+
static const char * const rtd1625_iso_ai_tdm0_groups[] = {
837
+
"gpio_100", "gpio_101", "gpio_102", "gpio_98"
838
+
};
839
+
840
+
static const char * const rtd1625_iso_vtc_i2s_groups[] = {
841
+
"gpio_100", "gpio_101", "gpio_102", "gpio_161", "gpio_98"
842
+
};
843
+
844
+
static const char * const rtd1625_iso_ai_i2s0_groups[] = {
845
+
"gpio_100", "gpio_101", "gpio_102", "gpio_156", "gpio_160", "gpio_161",
846
+
"gpio_98"
847
+
};
848
+
849
+
static const char * const rtd1625_iso_ao_tdm0_groups[] = {
850
+
"gpio_100", "gpio_101", "gpio_102", "gpio_99"
851
+
};
852
+
853
+
static const char * const rtd1625_iso_ao_i2s0_groups[] = {
854
+
"gpio_100", "gpio_101", "gpio_102", "gpio_112", "gpio_99"
855
+
};
856
+
857
+
static const char * const rtd1625_iso_ai_tdm1_groups[] = {
858
+
"gpio_103", "gpio_105", "gpio_106", "gpio_107"
859
+
};
860
+
861
+
static const char * const rtd1625_iso_ai_i2s1_loc0_groups[] = {
862
+
"ai_i2s1_loc", "gpio_103", "gpio_105", "gpio_106", "gpio_107"
863
+
};
864
+
865
+
static const char * const rtd1625_iso_ao_i2s0_loc1_groups[] = {
866
+
"gpio_103", "gpio_107"
867
+
};
868
+
869
+
static const char * const rtd1625_iso_ao_tdm1_loc0_groups[] = {
870
+
"gpio_104"
871
+
};
872
+
873
+
static const char * const rtd1625_iso_ao_i2s1_loc0_groups[] = {
874
+
"ao_i2s1_loc", "gpio_104", "gpio_105", "gpio_106", "gpio_107"
875
+
};
876
+
877
+
static const char * const rtd1625_iso_ao_tdm1_groups[] = {
878
+
"gpio_105", "gpio_106", "gpio_107"
879
+
};
880
+
881
+
static const char * const rtd1625_iso_ai_tdm2_groups[] = {
882
+
"gpio_108", "gpio_110", "gpio_111", "gpio_112"
883
+
};
884
+
885
+
static const char * const rtd1625_iso_pcm_groups[] = {
886
+
"gpio_108", "gpio_109", "gpio_110", "gpio_111"
887
+
};
888
+
889
+
static const char * const rtd1625_iso_ai_i2s2_groups[] = {
890
+
"gpio_108", "gpio_110", "gpio_111", "gpio_112"
891
+
};
892
+
893
+
static const char * const rtd1625_iso_ao_tdm2_groups[] = {
894
+
"gpio_109", "gpio_110", "gpio_111", "gpio_112"
895
+
};
896
+
897
+
static const char * const rtd1625_iso_ao_i2s2_groups[] = {
898
+
"gpio_109", "gpio_110", "gpio_111", "gpio_112"
899
+
};
900
+
901
+
static const char * const rtd1625_iso_vtc_ao_i2s_groups[] = {
902
+
"gpio_109", "gpio_110", "gpio_111", "gpio_112"
903
+
};
904
+
905
+
static const char * const rtd1625_iso_scpu_ejtag_loc0_groups[] = {
906
+
"ejtag_scpu_loc", "gpio_112"
907
+
};
908
+
909
+
static const char * const rtd1625_iso_acpu_ejtag_loc0_groups[] = {
910
+
"ejtag_acpu_loc", "gpio_112"
911
+
};
912
+
913
+
static const char * const rtd1625_iso_pcpu_ejtag_loc0_groups[] = {
914
+
"ejtag_pcpu_loc", "gpio_112"
915
+
};
916
+
917
+
static const char * const rtd1625_iso_aucpu0_ejtag_loc0_groups[] = {
918
+
"ejtag_aucpu0_loc", "gpio_112"
919
+
};
920
+
921
+
static const char * const rtd1625_iso_ve2_ejtag_loc0_groups[] = {
922
+
"ejtag_ve2_loc", "gpio_112"
923
+
};
924
+
925
+
static const char * const rtd1625_iso_gpu_ejtag_loc0_groups[] = {
926
+
"gpio_112"
927
+
};
928
+
929
+
static const char * const rtd1625_iso_ao_tdm1_loc1_groups[] = {
930
+
"gpio_112"
931
+
};
932
+
933
+
static const char * const rtd1625_iso_aucpu1_ejtag_loc0_groups[] = {
934
+
"ejtag_aucpu1_loc", "gpio_112"
935
+
};
936
+
937
+
static const char * const rtd1625_iso_edptx_hdp_groups[] = {
938
+
"gpio_128"
939
+
};
940
+
941
+
static const char * const rtd1625_iso_pwm5_groups[] = {
942
+
"gpio_130"
943
+
};
944
+
945
+
static const char * const rtd1625_iso_vi0_dtv_groups[] = {
946
+
"gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149", "gpio_150",
947
+
"gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155", "gpio_156",
948
+
"gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161"
949
+
};
950
+
951
+
static const char * const rtd1625_iso_vi1_dtv_groups[] = {
952
+
"gpio_154", "gpio_155", "gpio_156", "gpio_157", "gpio_158", "gpio_159",
953
+
"gpio_160", "gpio_161", "gpio_162"
954
+
};
955
+
956
+
static const char * const rtd1625_iso_ao_i2s0_loc0_groups[] = {
957
+
"gpio_154", "gpio_155"
958
+
};
959
+
960
+
static const char * const rtd1625_iso_dmic0_groups[] = {
961
+
"gpio_156", "gpio_157"
962
+
};
963
+
964
+
static const char * const rtd1625_iso_vtc_dmic_groups[] = {
965
+
"gpio_156", "gpio_157", "gpio_158", "gpio_159"
966
+
};
967
+
968
+
static const char * const rtd1625_iso_ai_i2s1_loc1_groups[] = {
969
+
"ai_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_160"
970
+
};
971
+
972
+
static const char * const rtd1625_iso_ao_i2s1_loc1_groups[] = {
973
+
"ao_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_161"
974
+
};
975
+
976
+
static const char * const rtd1625_iso_dmic1_groups[] = {
977
+
"gpio_158", "gpio_159"
978
+
};
979
+
980
+
static const char * const rtd1625_iso_dmic2_groups[] = {
981
+
"gpio_160", "gpio_161"
982
+
};
983
+
984
+
static const char * const rtd1625_iso_pwm0_loc2_groups[] = {
985
+
"gpio_162"
986
+
};
987
+
988
+
static const char * const rtd1625_iso_spdif_in_coaxial_groups[] = {
989
+
"gpio_163", "spdif_sel", "spdif_in_mode"
990
+
};
991
+
992
+
static const char * const rtd1625_iso_spdif_in_gpio_groups[] = {
993
+
"spdif_in_mode"
994
+
};
995
+
996
+
static const char * const rtd1625_iso_hi_width_disable_groups[] = {
997
+
"hi_width"
998
+
};
999
+
1000
+
static const char * const rtd1625_iso_hi_width_1bit_groups[] = {
1001
+
"hi_width"
1002
+
};
1003
+
1004
+
static const char * const rtd1625_iso_sf_disable_groups[] = {
1005
+
"sf_en"
1006
+
};
1007
+
1008
+
static const char * const rtd1625_iso_sf_enable_groups[] = {
1009
+
"sf_en"
1010
+
};
1011
+
1012
+
static const char * const rtd1625_iso_arm_trace_debug_disable_groups[] = {
1013
+
"arm_trace_dbg_en"
1014
+
};
1015
+
1016
+
static const char * const rtd1625_iso_arm_trace_debug_enable_groups[] = {
1017
+
"arm_trace_dbg_en"
1018
+
};
1019
+
1020
+
static const char * const rtd1625_iso_aucpu0_ejtag_loc1_groups[] = {
1021
+
"ejtag_aucpu0_loc"
1022
+
};
1023
+
1024
+
static const char * const rtd1625_iso_aucpu1_ejtag_loc1_groups[] = {
1025
+
"ejtag_aucpu1_loc"
1026
+
};
1027
+
1028
+
static const char * const rtd1625_iso_ve2_ejtag_loc1_groups[] = {
1029
+
"ejtag_ve2_loc"
1030
+
};
1031
+
1032
+
static const char * const rtd1625_iso_scpu_ejtag_loc1_groups[] = {
1033
+
"ejtag_scpu_loc"
1034
+
};
1035
+
1036
+
static const char * const rtd1625_iso_pcpu_ejtag_loc1_groups[] = {
1037
+
"ejtag_pcpu_loc"
1038
+
};
1039
+
1040
+
static const char * const rtd1625_iso_acpu_ejtag_loc1_groups[] = {
1041
+
"ejtag_acpu_loc"
1042
+
};
1043
+
1044
+
static const char * const rtd1625_iso_i2c6_loc0_groups[] = {
1045
+
"i2c6_loc"
1046
+
};
1047
+
1048
+
static const char * const rtd1625_iso_i2c6_loc1_groups[] = {
1049
+
"i2c6_loc"
1050
+
};
1051
+
1052
+
static const char * const rtd1625_iso_uart0_loc0_groups[] = {
1053
+
"uart0_loc"
1054
+
};
1055
+
1056
+
static const char * const rtd1625_iso_uart0_loc1_groups[] = {
1057
+
"uart0_loc"
1058
+
};
1059
+
1060
+
static const char * const rtd1625_iso_etn_phy_loc0_groups[] = {
1061
+
"etn_phy_loc"
1062
+
};
1063
+
1064
+
static const char * const rtd1625_iso_etn_phy_loc1_groups[] = {
1065
+
"etn_phy_loc"
1066
+
};
1067
+
1068
+
static const char * const rtd1625_iso_spdif_loc0_groups[] = {
1069
+
"spdif_loc"
1070
+
};
1071
+
1072
+
static const char * const rtd1625_iso_spdif_loc1_groups[] = {
1073
+
"spdif_loc"
1074
+
};
1075
+
1076
+
static const char * const rtd1625_iso_rgmii_1v2_groups[] = {
1077
+
"rgmii_vdsel"
1078
+
};
1079
+
1080
+
static const char * const rtd1625_iso_rgmii_1v8_groups[] = {
1081
+
"rgmii_vdsel"
1082
+
};
1083
+
1084
+
static const char * const rtd1625_iso_rgmii_2v5_groups[] = {
1085
+
"rgmii_vdsel"
1086
+
};
1087
+
1088
+
static const char * const rtd1625_iso_rgmii_3v3_groups[] = {
1089
+
"rgmii_vdsel"
1090
+
};
1091
+
1092
+
static const char * const rtd1625_iso_csi_1v2_groups[] = {
1093
+
"csi_vdsel"
1094
+
};
1095
+
1096
+
static const char * const rtd1625_iso_csi_1v8_groups[] = {
1097
+
"csi_vdsel"
1098
+
};
1099
+
1100
+
static const char * const rtd1625_iso_csi_2v5_groups[] = {
1101
+
"csi_vdsel"
1102
+
};
1103
+
1104
+
static const char * const rtd1625_iso_csi_3v3_groups[] = {
1105
+
"csi_vdsel"
1106
+
};
1107
+
1108
+
static const char * const rtd1625_isom_gpio_groups[] = {
1109
+
"gpio_0", "gpio_1", "gpio_28", "gpio_29"
1110
+
};
1111
+
1112
+
static const char * const rtd1625_isom_pctrl_groups[] = {
1113
+
"gpio_0", "gpio_1", "gpio_28", "gpio_29"
1114
+
};
1115
+
1116
+
static const char * const rtd1625_isom_iso_tristate_groups[] = {
1117
+
"gpio_0", "gpio_1", "gpio_28", "gpio_29"
1118
+
};
1119
+
1120
+
static const char * const rtd1625_isom_ir_rx_loc1_groups[] = {
1121
+
"gpio_1", "ir_rx_loc"
1122
+
};
1123
+
1124
+
static const char * const rtd1625_isom_uart10_groups[] = {
1125
+
"gpio_28", "gpio_29"
1126
+
};
1127
+
1128
+
static const char * const rtd1625_isom_isom_dbg_out_groups[] = {
1129
+
"gpio_28", "gpio_29"
1130
+
};
1131
+
1132
+
static const char * const rtd1625_isom_ir_rx_loc0_groups[] = {
1133
+
"gpio_29", "ir_rx_loc"
1134
+
};
1135
+
1136
+
static const char * const rtd1625_ve4_gpio_groups[] = {
1137
+
"gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135",
1138
+
"gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141",
1139
+
"gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165",
1140
+
"gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25",
1141
+
"gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35",
1142
+
"gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53",
1143
+
"gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6",
1144
+
"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93"
1145
+
};
1146
+
1147
+
static const char * const rtd1625_ve4_uart0_loc0_groups[] = {
1148
+
"gpio_2", "gpio_3"
1149
+
};
1150
+
1151
+
static const char * const rtd1625_ve4_iso_tristate_groups[] = {
1152
+
"gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135",
1153
+
"gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141",
1154
+
"gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165",
1155
+
"gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25",
1156
+
"gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35",
1157
+
"gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53",
1158
+
"gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6",
1159
+
"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93"
1160
+
};
1161
+
1162
+
static const char * const rtd1625_ve4_uart2_groups[] = {
1163
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1164
+
};
1165
+
1166
+
static const char * const rtd1625_ve4_gspi0_groups[] = {
1167
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1168
+
};
1169
+
1170
+
static const char * const rtd1625_ve4_scpu_ejtag_loc0_groups[] = {
1171
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1172
+
};
1173
+
1174
+
static const char * const rtd1625_ve4_acpu_ejtag_loc0_groups[] = {
1175
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1176
+
};
1177
+
1178
+
static const char * const rtd1625_ve4_pcpu_ejtag_loc0_groups[] = {
1179
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1180
+
};
1181
+
1182
+
static const char * const rtd1625_ve4_aucpu0_ejtag_loc0_groups[] = {
1183
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1184
+
};
1185
+
1186
+
static const char * const rtd1625_ve4_ve2_ejtag_loc0_groups[] = {
1187
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1188
+
};
1189
+
1190
+
static const char * const rtd1625_ve4_gpu_ejtag_loc0_groups[] = {
1191
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1192
+
};
1193
+
1194
+
static const char * const rtd1625_ve4_aucpu1_ejtag_loc0_groups[] = {
1195
+
"gpio_4", "gpio_5", "gpio_6", "gpio_7"
1196
+
};
1197
+
1198
+
static const char * const rtd1625_ve4_pwm0_loc1_groups[] = {
1199
+
"gpio_6"
1200
+
};
1201
+
1202
+
static const char * const rtd1625_ve4_pwm1_loc0_groups[] = {
1203
+
"gpio_7"
1204
+
};
1205
+
1206
+
static const char * const rtd1625_ve4_i2c0_groups[] = {
1207
+
"gpio_12", "gpio_13"
1208
+
};
1209
+
1210
+
static const char * const rtd1625_ve4_pwm0_loc3_groups[] = {
1211
+
"gpio_12"
1212
+
};
1213
+
1214
+
static const char * const rtd1625_ve4_dptx_hpd_groups[] = {
1215
+
"gpio_16"
1216
+
};
1217
+
1218
+
static const char * const rtd1625_ve4_pwm2_loc0_groups[] = {
1219
+
"gpio_16"
1220
+
};
1221
+
1222
+
static const char * const rtd1625_ve4_pcie0_groups[] = {
1223
+
"gpio_18"
1224
+
};
1225
+
1226
+
static const char * const rtd1625_ve4_pwm3_loc0_groups[] = {
1227
+
"gpio_19"
1228
+
};
1229
+
1230
+
static const char * const rtd1625_ve4_i2c3_groups[] = {
1231
+
"gpio_24", "gpio_25"
1232
+
};
1233
+
1234
+
static const char * const rtd1625_ve4_pcie1_groups[] = {
1235
+
"gpio_30"
1236
+
};
1237
+
1238
+
static const char * const rtd1625_ve4_uart9_groups[] = {
1239
+
"gpio_32", "gpio_33"
1240
+
};
1241
+
1242
+
static const char * const rtd1625_ve4_ve4_uart_loc2_groups[] = {
1243
+
"gpio_32", "gpio_33", "ve4_uart_loc"
1244
+
};
1245
+
1246
+
static const char * const rtd1625_ve4_sd_groups[] = {
1247
+
"gpio_42", "gpio_43"
1248
+
};
1249
+
1250
+
static const char * const rtd1625_ve4_i2c6_loc1_groups[] = {
1251
+
"gpio_51", "gpio_61"
1252
+
};
1253
+
1254
+
static const char * const rtd1625_ve4_uart3_groups[] = {
1255
+
"gpio_53", "gpio_54", "gpio_55", "gpio_56"
1256
+
};
1257
+
1258
+
static const char * const rtd1625_ve4_ts0_groups[] = {
1259
+
"gpio_53", "gpio_54", "gpio_55", "gpio_56"
1260
+
};
1261
+
1262
+
static const char * const rtd1625_ve4_gspi2_groups[] = {
1263
+
"gpio_53", "gpio_54", "gpio_55", "gpio_56"
1264
+
};
1265
+
1266
+
static const char * const rtd1625_ve4_ve4_uart_loc0_groups[] = {
1267
+
"gpio_53", "gpio_54", "ve4_uart_loc"
1268
+
};
1269
+
1270
+
static const char * const rtd1625_ve4_uart5_groups[] = {
1271
+
"gpio_57", "gpio_58"
1272
+
};
1273
+
1274
+
static const char * const rtd1625_ve4_uart0_loc1_groups[] = {
1275
+
"gpio_57", "gpio_58"
1276
+
};
1277
+
1278
+
static const char * const rtd1625_ve4_gspi1_groups[] = {
1279
+
"gpio_57", "gpio_58", "gpio_59", "gpio_60"
1280
+
};
1281
+
1282
+
static const char * const rtd1625_ve4_uart4_groups[] = {
1283
+
"gpio_59", "gpio_60"
1284
+
};
1285
+
1286
+
static const char * const rtd1625_ve4_i2c4_groups[] = {
1287
+
"gpio_59", "gpio_60"
1288
+
};
1289
+
1290
+
static const char * const rtd1625_ve4_spdif_out_groups[] = {
1291
+
"gpio_61"
1292
+
};
1293
+
1294
+
static const char * const rtd1625_ve4_spdif_in_optical_groups[] = {
1295
+
"gpio_61"
1296
+
};
1297
+
1298
+
static const char * const rtd1625_ve4_pll_test_loc0_groups[] = {
1299
+
"gpio_62", "gpio_63"
1300
+
};
1301
+
1302
+
static const char * const rtd1625_ve4_uart6_groups[] = {
1303
+
"gpio_92", "gpio_93"
1304
+
};
1305
+
1306
+
static const char * const rtd1625_ve4_i2c7_groups[] = {
1307
+
"gpio_92", "gpio_93"
1308
+
};
1309
+
1310
+
static const char * const rtd1625_ve4_ve4_uart_loc1_groups[] = {
1311
+
"gpio_92", "gpio_93", "ve4_uart_loc"
1312
+
};
1313
+
1314
+
static const char * const rtd1625_ve4_pwm1_loc1_groups[] = {
1315
+
"gpio_93"
1316
+
};
1317
+
1318
+
static const char * const rtd1625_ve4_pwm6_groups[] = {
1319
+
"gpio_132"
1320
+
};
1321
+
1322
+
static const char * const rtd1625_ve4_ts1_groups[] = {
1323
+
"gpio_133", "gpio_134", "gpio_135", "gpio_136"
1324
+
};
1325
+
1326
+
static const char * const rtd1625_ve4_pwm0_loc0_groups[] = {
1327
+
"gpio_136"
1328
+
};
1329
+
1330
+
static const char * const rtd1625_ve4_i2c6_loc0_groups[] = {
1331
+
"gpio_137", "gpio_138"
1332
+
};
1333
+
1334
+
static const char * const rtd1625_ve4_csi0_groups[] = {
1335
+
"gpio_141"
1336
+
};
1337
+
1338
+
static const char * const rtd1625_ve4_csi1_groups[] = {
1339
+
"gpio_144"
1340
+
};
1341
+
1342
+
static const char * const rtd1625_ve4_etn_led_loc1_groups[] = {
1343
+
"gpio_164", "gpio_165"
1344
+
};
1345
+
1346
+
static const char * const rtd1625_ve4_etn_phy_loc1_groups[] = {
1347
+
"gpio_164", "gpio_165"
1348
+
};
1349
+
1350
+
static const char * const rtd1625_ve4_i2c5_groups[] = {
1351
+
"gpio_164", "gpio_165"
1352
+
};
1353
+
1354
+
static const char * const rtd1625_main2_gpio_groups[] = {
1355
+
"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
1356
+
"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
1357
+
"emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21",
1358
+
"gpio_22", "gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67",
1359
+
"gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86",
1360
+
"gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk",
1361
+
"hif_data", "hif_en", "hif_rdy"
1362
+
};
1363
+
1364
+
static const char * const rtd1625_main2_emmc_groups[] = {
1365
+
"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
1366
+
"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
1367
+
"emmc_dd_sb", "emmc_rst_n"
1368
+
};
1369
+
1370
+
static const char * const rtd1625_main2_iso_tristate_groups[] = {
1371
+
"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
1372
+
"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
1373
+
"emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21",
1374
+
"gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67", "gpio_80",
1375
+
"gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86", "gpio_87",
1376
+
"gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk", "hif_data", "hif_en",
1377
+
"hif_rdy"
1378
+
};
1379
+
1380
+
static const char * const rtd1625_main2_nf_groups[] = {
1381
+
"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
1382
+
"emmc_data_5"
1383
+
};
1384
+
1385
+
static const char * const rtd1625_main2_etn_led_loc0_groups[] = {
1386
+
"gpio_14", "gpio_15"
1387
+
};
1388
+
1389
+
static const char * const rtd1625_main2_etn_phy_loc0_groups[] = {
1390
+
"gpio_14", "gpio_15"
1391
+
};
1392
+
1393
+
static const char * const rtd1625_main2_rgmii_groups[] = {
1394
+
"gpio_14", "gpio_15", "gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84",
1395
+
"gpio_85", "gpio_86", "gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91"
1396
+
};
1397
+
1398
+
static const char * const rtd1625_main2_i2c1_groups[] = {
1399
+
"gpio_20", "gpio_21"
1400
+
};
1401
+
1402
+
static const char * const rtd1625_main2_dbg_out1_groups[] = {
1403
+
"gpio_22"
1404
+
};
1405
+
1406
+
static const char * const rtd1625_main2_sd_groups[] = {
1407
+
"gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1408
+
};
1409
+
1410
+
static const char * const rtd1625_main2_scpu_ejtag_loc1_groups[] = {
1411
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1412
+
};
1413
+
1414
+
static const char * const rtd1625_main2_acpu_ejtag_loc1_groups[] = {
1415
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1416
+
};
1417
+
1418
+
static const char * const rtd1625_main2_pcpu_ejtag_loc1_groups[] = {
1419
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1420
+
};
1421
+
1422
+
static const char * const rtd1625_main2_aupu0_ejtag_loc1_groups[] = {
1423
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1424
+
};
1425
+
1426
+
static const char * const rtd1625_main2_ve2_ejtag_loc1_groups[] = {
1427
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1428
+
};
1429
+
1430
+
static const char * const rtd1625_main2_hi_loc0_groups[] = {
1431
+
"hif_clk", "hif_data", "hif_en", "hif_rdy"
1432
+
};
1433
+
1434
+
static const char * const rtd1625_main2_hi_m_groups[] = {
1435
+
"hif_clk", "hif_data", "hif_en", "hif_rdy"
1436
+
};
1437
+
1438
+
static const char * const rtd1625_main2_aupu1_ejtag_loc1_groups[] = {
1439
+
"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
1440
+
};
1441
+
1442
+
static const char * const rtd1625_main2_spi_groups[] = {
1443
+
"gpio_64", "gpio_65", "gpio_66", "gpio_67"
1444
+
};
1445
+
1446
+
static const char * const rtd1625_main2_pll_test_loc1_groups[] = {
1447
+
"gpio_65", "gpio_66"
1448
+
};
1449
+
1450
+
static const char * const rtd1625_main2_rmii_groups[] = {
1451
+
"gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_87", "gpio_88",
1452
+
"gpio_89"
1453
+
};
1454
+
1455
+
#define RTD1625_FUNC(_group, _name) \
1456
+
{ \
1457
+
.name = # _name, \
1458
+
.groups = rtd1625_ ## _group ## _ ## _name ## _groups, \
1459
+
.num_groups = ARRAY_SIZE(rtd1625_ ## _group ## _ ## _name ## _groups), \
1460
+
}
1461
+
1462
+
static const struct rtd_pin_func_desc rtd1625_iso_pin_functions[] = {
1463
+
RTD1625_FUNC(iso, gpio),
1464
+
RTD1625_FUNC(iso, uart1),
1465
+
RTD1625_FUNC(iso, iso_tristate),
1466
+
RTD1625_FUNC(iso, usb_cc1),
1467
+
RTD1625_FUNC(iso, usb_cc2),
1468
+
RTD1625_FUNC(iso, sdio),
1469
+
RTD1625_FUNC(iso, scpu_ejtag_loc2),
1470
+
RTD1625_FUNC(iso, acpu_ejtag_loc2),
1471
+
RTD1625_FUNC(iso, pcpu_ejtag_loc2),
1472
+
RTD1625_FUNC(iso, aucpu0_ejtag_loc2),
1473
+
RTD1625_FUNC(iso, ve2_ejtag_loc2),
1474
+
RTD1625_FUNC(iso, aucpu1_ejtag_loc2),
1475
+
RTD1625_FUNC(iso, pwm4),
1476
+
RTD1625_FUNC(iso, uart7),
1477
+
RTD1625_FUNC(iso, pwm2_loc1),
1478
+
RTD1625_FUNC(iso, uart8),
1479
+
RTD1625_FUNC(iso, pwm3_loc1),
1480
+
RTD1625_FUNC(iso, ai_tdm0),
1481
+
RTD1625_FUNC(iso, vtc_i2s),
1482
+
RTD1625_FUNC(iso, ai_i2s0),
1483
+
RTD1625_FUNC(iso, ao_tdm0),
1484
+
RTD1625_FUNC(iso, ao_i2s0),
1485
+
RTD1625_FUNC(iso, ai_tdm1),
1486
+
RTD1625_FUNC(iso, ai_i2s1_loc0),
1487
+
RTD1625_FUNC(iso, ao_i2s0_loc1),
1488
+
RTD1625_FUNC(iso, ao_tdm1_loc0),
1489
+
RTD1625_FUNC(iso, ao_i2s1_loc0),
1490
+
RTD1625_FUNC(iso, ao_tdm1),
1491
+
RTD1625_FUNC(iso, ai_tdm2),
1492
+
RTD1625_FUNC(iso, pcm),
1493
+
RTD1625_FUNC(iso, ai_i2s2),
1494
+
RTD1625_FUNC(iso, ao_tdm2),
1495
+
RTD1625_FUNC(iso, ao_i2s2),
1496
+
RTD1625_FUNC(iso, vtc_ao_i2s),
1497
+
RTD1625_FUNC(iso, scpu_ejtag_loc0),
1498
+
RTD1625_FUNC(iso, acpu_ejtag_loc0),
1499
+
RTD1625_FUNC(iso, pcpu_ejtag_loc0),
1500
+
RTD1625_FUNC(iso, aucpu0_ejtag_loc0),
1501
+
RTD1625_FUNC(iso, ve2_ejtag_loc0),
1502
+
RTD1625_FUNC(iso, gpu_ejtag_loc0),
1503
+
RTD1625_FUNC(iso, ao_tdm1_loc1),
1504
+
RTD1625_FUNC(iso, aucpu1_ejtag_loc0),
1505
+
RTD1625_FUNC(iso, edptx_hdp),
1506
+
RTD1625_FUNC(iso, pwm5),
1507
+
RTD1625_FUNC(iso, vi0_dtv),
1508
+
RTD1625_FUNC(iso, vi1_dtv),
1509
+
RTD1625_FUNC(iso, ao_i2s0_loc0),
1510
+
RTD1625_FUNC(iso, dmic0),
1511
+
RTD1625_FUNC(iso, vtc_dmic),
1512
+
RTD1625_FUNC(iso, ai_i2s1_loc1),
1513
+
RTD1625_FUNC(iso, ao_i2s1_loc1),
1514
+
RTD1625_FUNC(iso, dmic1),
1515
+
RTD1625_FUNC(iso, dmic2),
1516
+
RTD1625_FUNC(iso, pwm0_loc2),
1517
+
RTD1625_FUNC(iso, spdif_in_coaxial),
1518
+
RTD1625_FUNC(iso, spdif_in_gpio),
1519
+
RTD1625_FUNC(iso, hi_width_disable),
1520
+
RTD1625_FUNC(iso, hi_width_1bit),
1521
+
RTD1625_FUNC(iso, sf_disable),
1522
+
RTD1625_FUNC(iso, sf_enable),
1523
+
RTD1625_FUNC(iso, arm_trace_debug_disable),
1524
+
RTD1625_FUNC(iso, arm_trace_debug_enable),
1525
+
RTD1625_FUNC(iso, aucpu0_ejtag_loc1),
1526
+
RTD1625_FUNC(iso, aucpu1_ejtag_loc1),
1527
+
RTD1625_FUNC(iso, ve2_ejtag_loc1),
1528
+
RTD1625_FUNC(iso, scpu_ejtag_loc1),
1529
+
RTD1625_FUNC(iso, pcpu_ejtag_loc1),
1530
+
RTD1625_FUNC(iso, acpu_ejtag_loc1),
1531
+
RTD1625_FUNC(iso, i2c6_loc0),
1532
+
RTD1625_FUNC(iso, i2c6_loc1),
1533
+
RTD1625_FUNC(iso, uart0_loc0),
1534
+
RTD1625_FUNC(iso, uart0_loc1),
1535
+
RTD1625_FUNC(iso, etn_phy_loc0),
1536
+
RTD1625_FUNC(iso, etn_phy_loc1),
1537
+
RTD1625_FUNC(iso, spdif_loc0),
1538
+
RTD1625_FUNC(iso, spdif_loc1),
1539
+
RTD1625_FUNC(iso, rgmii_1v2),
1540
+
RTD1625_FUNC(iso, rgmii_1v8),
1541
+
RTD1625_FUNC(iso, rgmii_2v5),
1542
+
RTD1625_FUNC(iso, rgmii_3v3),
1543
+
RTD1625_FUNC(iso, csi_1v2),
1544
+
RTD1625_FUNC(iso, csi_1v8),
1545
+
RTD1625_FUNC(iso, csi_2v5),
1546
+
RTD1625_FUNC(iso, csi_3v3),
1547
+
};
1548
+
1549
+
static const struct rtd_pin_func_desc rtd1625_isom_pin_functions[] = {
1550
+
RTD1625_FUNC(isom, gpio),
1551
+
RTD1625_FUNC(isom, pctrl),
1552
+
RTD1625_FUNC(isom, iso_tristate),
1553
+
RTD1625_FUNC(isom, ir_rx_loc1),
1554
+
RTD1625_FUNC(isom, uart10),
1555
+
RTD1625_FUNC(isom, isom_dbg_out),
1556
+
RTD1625_FUNC(isom, ir_rx_loc0),
1557
+
};
1558
+
1559
+
static const struct rtd_pin_func_desc rtd1625_ve4_pin_functions[] = {
1560
+
RTD1625_FUNC(ve4, gpio),
1561
+
RTD1625_FUNC(ve4, uart0_loc0),
1562
+
RTD1625_FUNC(ve4, iso_tristate),
1563
+
RTD1625_FUNC(ve4, uart2),
1564
+
RTD1625_FUNC(ve4, gspi0),
1565
+
RTD1625_FUNC(ve4, scpu_ejtag_loc0),
1566
+
RTD1625_FUNC(ve4, acpu_ejtag_loc0),
1567
+
RTD1625_FUNC(ve4, pcpu_ejtag_loc0),
1568
+
RTD1625_FUNC(ve4, aucpu0_ejtag_loc0),
1569
+
RTD1625_FUNC(ve4, ve2_ejtag_loc0),
1570
+
RTD1625_FUNC(ve4, gpu_ejtag_loc0),
1571
+
RTD1625_FUNC(ve4, aucpu1_ejtag_loc0),
1572
+
RTD1625_FUNC(ve4, pwm0_loc1),
1573
+
RTD1625_FUNC(ve4, pwm1_loc0),
1574
+
RTD1625_FUNC(ve4, i2c0),
1575
+
RTD1625_FUNC(ve4, pwm0_loc3),
1576
+
RTD1625_FUNC(ve4, dptx_hpd),
1577
+
RTD1625_FUNC(ve4, pwm2_loc0),
1578
+
RTD1625_FUNC(ve4, pcie0),
1579
+
RTD1625_FUNC(ve4, pwm3_loc0),
1580
+
RTD1625_FUNC(ve4, i2c3),
1581
+
RTD1625_FUNC(ve4, pcie1),
1582
+
RTD1625_FUNC(ve4, uart9),
1583
+
RTD1625_FUNC(ve4, ve4_uart_loc2),
1584
+
RTD1625_FUNC(ve4, sd),
1585
+
RTD1625_FUNC(ve4, i2c6_loc1),
1586
+
RTD1625_FUNC(ve4, uart3),
1587
+
RTD1625_FUNC(ve4, ts0),
1588
+
RTD1625_FUNC(ve4, gspi2),
1589
+
RTD1625_FUNC(ve4, ve4_uart_loc0),
1590
+
RTD1625_FUNC(ve4, uart5),
1591
+
RTD1625_FUNC(ve4, uart0_loc1),
1592
+
RTD1625_FUNC(ve4, gspi1),
1593
+
RTD1625_FUNC(ve4, uart4),
1594
+
RTD1625_FUNC(ve4, i2c4),
1595
+
RTD1625_FUNC(ve4, spdif_out),
1596
+
RTD1625_FUNC(ve4, spdif_in_optical),
1597
+
RTD1625_FUNC(ve4, pll_test_loc0),
1598
+
RTD1625_FUNC(ve4, uart6),
1599
+
RTD1625_FUNC(ve4, i2c7),
1600
+
RTD1625_FUNC(ve4, ve4_uart_loc1),
1601
+
RTD1625_FUNC(ve4, pwm1_loc1),
1602
+
RTD1625_FUNC(ve4, pwm6),
1603
+
RTD1625_FUNC(ve4, ts1),
1604
+
RTD1625_FUNC(ve4, pwm0_loc0),
1605
+
RTD1625_FUNC(ve4, i2c6_loc0),
1606
+
RTD1625_FUNC(ve4, csi0),
1607
+
RTD1625_FUNC(ve4, csi1),
1608
+
RTD1625_FUNC(ve4, etn_led_loc1),
1609
+
RTD1625_FUNC(ve4, etn_phy_loc1),
1610
+
RTD1625_FUNC(ve4, i2c5),
1611
+
};
1612
+
1613
+
static const struct rtd_pin_func_desc rtd1625_main2_pin_functions[] = {
1614
+
RTD1625_FUNC(main2, gpio),
1615
+
RTD1625_FUNC(main2, emmc),
1616
+
RTD1625_FUNC(main2, iso_tristate),
1617
+
RTD1625_FUNC(main2, nf),
1618
+
RTD1625_FUNC(main2, etn_led_loc0),
1619
+
RTD1625_FUNC(main2, etn_phy_loc0),
1620
+
RTD1625_FUNC(main2, rgmii),
1621
+
RTD1625_FUNC(main2, i2c1),
1622
+
RTD1625_FUNC(main2, dbg_out1),
1623
+
RTD1625_FUNC(main2, sd),
1624
+
RTD1625_FUNC(main2, scpu_ejtag_loc1),
1625
+
RTD1625_FUNC(main2, acpu_ejtag_loc1),
1626
+
RTD1625_FUNC(main2, pcpu_ejtag_loc1),
1627
+
RTD1625_FUNC(main2, aupu0_ejtag_loc1),
1628
+
RTD1625_FUNC(main2, ve2_ejtag_loc1),
1629
+
RTD1625_FUNC(main2, hi_loc0),
1630
+
RTD1625_FUNC(main2, hi_m),
1631
+
RTD1625_FUNC(main2, aupu1_ejtag_loc1),
1632
+
RTD1625_FUNC(main2, spi),
1633
+
RTD1625_FUNC(main2, pll_test_loc1),
1634
+
RTD1625_FUNC(main2, rmii),
1635
+
};
1636
+
1637
+
#undef RTD1625_FUNC
1638
+
1639
+
static const struct rtd_pin_desc rtd1625_iso_muxes[] = {
1640
+
[RTD1625_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x0, GENMASK(3, 0),
1641
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1642
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
1643
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1644
+
),
1645
+
[RTD1625_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x0, GENMASK(7, 4),
1646
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1647
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
1648
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1649
+
),
1650
+
[RTD1625_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x0, GENMASK(11, 8),
1651
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1652
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
1653
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1654
+
),
1655
+
[RTD1625_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x0, GENMASK(15, 12),
1656
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1657
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
1658
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1659
+
),
1660
+
[RTD1625_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x0, GENMASK(19, 16),
1661
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
1662
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "usb_cc1"),
1663
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
1664
+
),
1665
+
[RTD1625_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x0, GENMASK(23, 20),
1666
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
1667
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"),
1668
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
1669
+
),
1670
+
[RTD1625_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x0, GENMASK(27, 24),
1671
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
1672
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sdio"),
1673
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "scpu_ejtag_loc2"),
1674
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "acpu_ejtag_loc2"),
1675
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "pcpu_ejtag_loc2"),
1676
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "aucpu0_ejtag_loc2"),
1677
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "ve2_ejtag_loc2"),
1678
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "aucpu1_ejtag_loc2"),
1679
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
1680
+
),
1681
+
[RTD1625_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x0, GENMASK(31, 28),
1682
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
1683
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sdio"),
1684
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "scpu_ejtag_loc2"),
1685
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "acpu_ejtag_loc2"),
1686
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "pcpu_ejtag_loc2"),
1687
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "aucpu0_ejtag_loc2"),
1688
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "ve2_ejtag_loc2"),
1689
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "aucpu1_ejtag_loc2"),
1690
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
1691
+
),
1692
+
1693
+
[RTD1625_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x4, GENMASK(3, 0),
1694
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1695
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sdio"),
1696
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc2"),
1697
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc2"),
1698
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc2"),
1699
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc2"),
1700
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc2"),
1701
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "aucpu1_ejtag_loc2"),
1702
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1703
+
),
1704
+
[RTD1625_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x4, GENMASK(7, 4),
1705
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1706
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio"),
1707
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc2"),
1708
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc2"),
1709
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc2"),
1710
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aucpu0_ejtag_loc2"),
1711
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc2"),
1712
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aucpu1_ejtag_loc2"),
1713
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1714
+
),
1715
+
[RTD1625_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x4, GENMASK(11, 8),
1716
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1717
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sdio"),
1718
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc2"),
1719
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc2"),
1720
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc2"),
1721
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc2"),
1722
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc2"),
1723
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc2"),
1724
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1725
+
),
1726
+
[RTD1625_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x4, GENMASK(15, 12),
1727
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1728
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sdio"),
1729
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1730
+
),
1731
+
[RTD1625_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x4, GENMASK(19, 16),
1732
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
1733
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm4"),
1734
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
1735
+
),
1736
+
[RTD1625_ISO_GPIO_94] = RTK_PIN_MUX(gpio_94, 0x4, GENMASK(23, 20),
1737
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
1738
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart7"),
1739
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
1740
+
),
1741
+
[RTD1625_ISO_GPIO_95] = RTK_PIN_MUX(gpio_95, 0x4, GENMASK(27, 24),
1742
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
1743
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart7"),
1744
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm2_loc1"),
1745
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
1746
+
),
1747
+
[RTD1625_ISO_GPIO_96] = RTK_PIN_MUX(gpio_96, 0x4, GENMASK(31, 28),
1748
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
1749
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart8"),
1750
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
1751
+
),
1752
+
1753
+
[RTD1625_ISO_GPIO_97] = RTK_PIN_MUX(gpio_97, 0x8, GENMASK(3, 0),
1754
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1755
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart8"),
1756
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "pwm3_loc1"),
1757
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1758
+
),
1759
+
[RTD1625_ISO_GPIO_98] = RTK_PIN_MUX(gpio_98, 0x8, GENMASK(7, 4),
1760
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1761
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm0"),
1762
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "vtc_i2s"),
1763
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"),
1764
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1765
+
),
1766
+
[RTD1625_ISO_GPIO_99] = RTK_PIN_MUX(gpio_99, 0x8, GENMASK(11, 8),
1767
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1768
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm0"),
1769
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s0"),
1770
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1771
+
),
1772
+
[RTD1625_ISO_GPIO_100] = RTK_PIN_MUX(gpio_100, 0x8, GENMASK(15, 12),
1773
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1774
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm0"),
1775
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ao_tdm0"),
1776
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "vtc_i2s"),
1777
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_i2s0"),
1778
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s0"),
1779
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1780
+
),
1781
+
[RTD1625_ISO_GPIO_101] = RTK_PIN_MUX(gpio_101, 0x8, GENMASK(19, 16),
1782
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
1783
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "ai_tdm0"),
1784
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm0"),
1785
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "vtc_i2s"),
1786
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_i2s0"),
1787
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s0"),
1788
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
1789
+
),
1790
+
[RTD1625_ISO_GPIO_102] = RTK_PIN_MUX(gpio_102, 0x8, GENMASK(23, 20),
1791
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
1792
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm0"),
1793
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm0"),
1794
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "vtc_i2s"),
1795
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"),
1796
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s0"),
1797
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
1798
+
),
1799
+
[RTD1625_ISO_GPIO_103] = RTK_PIN_MUX(gpio_103, 0x8, GENMASK(27, 24),
1800
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
1801
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm1"),
1802
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s1_loc0"),
1803
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s0_loc1"),
1804
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
1805
+
),
1806
+
[RTD1625_ISO_GPIO_104] = RTK_PIN_MUX(gpio_104, 0x8, GENMASK(31, 28),
1807
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
1808
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao_tdm1_loc0"),
1809
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s1_loc0"),
1810
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
1811
+
),
1812
+
1813
+
[RTD1625_ISO_GPIO_105] = RTK_PIN_MUX(gpio_105, 0xc, GENMASK(3, 0),
1814
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1815
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm1"),
1816
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm1"),
1817
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s1_loc0"),
1818
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s1_loc0"),
1819
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1820
+
),
1821
+
[RTD1625_ISO_GPIO_106] = RTK_PIN_MUX(gpio_106, 0xc, GENMASK(7, 4),
1822
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1823
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm1"),
1824
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ao_tdm1"),
1825
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "ai_i2s1_loc0"),
1826
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "ao_i2s1_loc0"),
1827
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1828
+
),
1829
+
[RTD1625_ISO_GPIO_107] = RTK_PIN_MUX(gpio_107, 0xc, GENMASK(11, 8),
1830
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1831
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_tdm1"),
1832
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm1"),
1833
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc0"),
1834
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc0"),
1835
+
RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "ao_i2s0_loc1"),
1836
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1837
+
),
1838
+
[RTD1625_ISO_GPIO_108] = RTK_PIN_MUX(gpio_108, 0xc, GENMASK(15, 12),
1839
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1840
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm2"),
1841
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "pcm"),
1842
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s2"),
1843
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1844
+
),
1845
+
[RTD1625_ISO_GPIO_109] = RTK_PIN_MUX(gpio_109, 0xc, GENMASK(19, 16),
1846
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
1847
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm2"),
1848
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "pcm"),
1849
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s2"),
1850
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "vtc_ao_i2s"),
1851
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
1852
+
),
1853
+
[RTD1625_ISO_GPIO_110] = RTK_PIN_MUX(gpio_110, 0xc, GENMASK(23, 20),
1854
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
1855
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm2"),
1856
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm2"),
1857
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "pcm"),
1858
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s2"),
1859
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s2"),
1860
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "vtc_ao_i2s"),
1861
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
1862
+
),
1863
+
[RTD1625_ISO_GPIO_111] = RTK_PIN_MUX(gpio_111, 0xc, GENMASK(27, 24),
1864
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
1865
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm2"),
1866
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao_tdm2"),
1867
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcm"),
1868
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s2"),
1869
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s2"),
1870
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "vtc_ao_i2s"),
1871
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
1872
+
),
1873
+
1874
+
[RTD1625_ISO_GPIO_112] = RTK_PIN_MUX(gpio_112, 0x10, GENMASK(4, 0),
1875
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1876
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm2"),
1877
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm2"),
1878
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc0"),
1879
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc0"),
1880
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc0"),
1881
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc0"),
1882
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc0"),
1883
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s2"),
1884
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s2"),
1885
+
RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "gpu_ejtag_loc0"),
1886
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "vtc_ao_i2s"),
1887
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate"),
1888
+
RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "ao_tdm1_loc1"),
1889
+
RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "aucpu1_ejtag_loc0"),
1890
+
RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "ao_i2s0")
1891
+
),
1892
+
[RTD1625_ISO_GPIO_128] = RTK_PIN_MUX(gpio_128, 0x10, GENMASK(8, 5),
1893
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"),
1894
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "edptx_hdp"),
1895
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 5), "iso_tristate")
1896
+
),
1897
+
[RTD1625_ISO_GPIO_129] = RTK_PIN_MUX(gpio_129, 0x10, GENMASK(12, 9),
1898
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"),
1899
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 9), "iso_tristate")
1900
+
),
1901
+
[RTD1625_ISO_GPIO_130] = RTK_PIN_MUX(gpio_130, 0x10, GENMASK(16, 13),
1902
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
1903
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 13), "pwm5"),
1904
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 13), "iso_tristate")
1905
+
),
1906
+
[RTD1625_ISO_GPIO_131] = RTK_PIN_MUX(gpio_131, 0x10, GENMASK(20, 17),
1907
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "gpio"),
1908
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 17), "iso_tristate")
1909
+
),
1910
+
[RTD1625_ISO_GPIO_145] = RTK_PIN_MUX(gpio_145, 0x10, GENMASK(24, 21),
1911
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
1912
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "vi0_dtv"),
1913
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate")
1914
+
),
1915
+
[RTD1625_ISO_GPIO_146] = RTK_PIN_MUX(gpio_146, 0x10, GENMASK(28, 25),
1916
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
1917
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "vi0_dtv"),
1918
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate")
1919
+
),
1920
+
1921
+
[RTD1625_ISO_GPIO_147] = RTK_PIN_MUX(gpio_147, 0x14, GENMASK(3, 0),
1922
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1923
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"),
1924
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1925
+
),
1926
+
[RTD1625_ISO_GPIO_148] = RTK_PIN_MUX(gpio_148, 0x14, GENMASK(7, 4),
1927
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1928
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"),
1929
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1930
+
),
1931
+
[RTD1625_ISO_GPIO_149] = RTK_PIN_MUX(gpio_149, 0x14, GENMASK(11, 8),
1932
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1933
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"),
1934
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1935
+
),
1936
+
[RTD1625_ISO_GPIO_150] = RTK_PIN_MUX(gpio_150, 0x14, GENMASK(15, 12),
1937
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1938
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"),
1939
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1940
+
),
1941
+
[RTD1625_ISO_GPIO_151] = RTK_PIN_MUX(gpio_151, 0x14, GENMASK(19, 16),
1942
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
1943
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"),
1944
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
1945
+
),
1946
+
[RTD1625_ISO_GPIO_152] = RTK_PIN_MUX(gpio_152, 0x14, GENMASK(23, 20),
1947
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
1948
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"),
1949
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
1950
+
),
1951
+
[RTD1625_ISO_GPIO_153] = RTK_PIN_MUX(gpio_153, 0x14, GENMASK(27, 24),
1952
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
1953
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"),
1954
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
1955
+
),
1956
+
[RTD1625_ISO_GPIO_154] = RTK_PIN_MUX(gpio_154, 0x14, GENMASK(31, 28),
1957
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
1958
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "vi0_dtv"),
1959
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"),
1960
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s0_loc0"),
1961
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
1962
+
),
1963
+
1964
+
[RTD1625_ISO_GPIO_155] = RTK_PIN_MUX(gpio_155, 0x18, GENMASK(3, 0),
1965
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
1966
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"),
1967
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vi1_dtv"),
1968
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s0_loc0"),
1969
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
1970
+
),
1971
+
[RTD1625_ISO_GPIO_156] = RTK_PIN_MUX(gpio_156, 0x18, GENMASK(7, 4),
1972
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
1973
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"),
1974
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vi1_dtv"),
1975
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic0"),
1976
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "vtc_dmic"),
1977
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"),
1978
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
1979
+
),
1980
+
[RTD1625_ISO_GPIO_157] = RTK_PIN_MUX(gpio_157, 0x18, GENMASK(11, 8),
1981
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
1982
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"),
1983
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vi1_dtv"),
1984
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic0"),
1985
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "vtc_dmic"),
1986
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc1"),
1987
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc1"),
1988
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
1989
+
),
1990
+
[RTD1625_ISO_GPIO_158] = RTK_PIN_MUX(gpio_158, 0x18, GENMASK(15, 12),
1991
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
1992
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"),
1993
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vi1_dtv"),
1994
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic1"),
1995
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "vtc_dmic"),
1996
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s1_loc1"),
1997
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s1_loc1"),
1998
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
1999
+
),
2000
+
[RTD1625_ISO_GPIO_159] = RTK_PIN_MUX(gpio_159, 0x18, GENMASK(19, 16),
2001
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2002
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"),
2003
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vi1_dtv"),
2004
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic1"),
2005
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "vtc_dmic"),
2006
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "ai_i2s1_loc1"),
2007
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s1_loc1"),
2008
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2009
+
),
2010
+
[RTD1625_ISO_GPIO_160] = RTK_PIN_MUX(gpio_160, 0x18, GENMASK(23, 20),
2011
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2012
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"),
2013
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vi1_dtv"),
2014
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic2"),
2015
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"),
2016
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s1_loc1"),
2017
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2018
+
),
2019
+
[RTD1625_ISO_GPIO_161] = RTK_PIN_MUX(gpio_161, 0x18, GENMASK(27, 24),
2020
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2021
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"),
2022
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "vi1_dtv"),
2023
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic2"),
2024
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "vtc_i2s"),
2025
+
RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_i2s0"),
2026
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s1_loc1"),
2027
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2028
+
),
2029
+
[RTD1625_ISO_GPIO_162] = RTK_PIN_MUX(gpio_162, 0x18, GENMASK(31, 28),
2030
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2031
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"),
2032
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm0_loc2"),
2033
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2034
+
),
2035
+
2036
+
[RTD1625_ISO_GPIO_163] = RTK_PIN_MUX(gpio_163, 0x1c, GENMASK(3, 0),
2037
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2038
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "spdif_in_coaxial"),
2039
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2040
+
),
2041
+
2042
+
[RTD1625_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
2043
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
2044
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")
2045
+
),
2046
+
[RTD1625_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
2047
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
2048
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")
2049
+
),
2050
+
[RTD1625_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(13, 12),
2051
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
2052
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")
2053
+
),
2054
+
[RTD1625_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x120, GENMASK(16, 14),
2055
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu0_ejtag_loc0"),
2056
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu0_ejtag_loc1"),
2057
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu0_ejtag_loc2")
2058
+
),
2059
+
[RTD1625_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x120, GENMASK(19, 17),
2060
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "aucpu1_ejtag_loc0"),
2061
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "aucpu1_ejtag_loc1"),
2062
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "aucpu1_ejtag_loc2")
2063
+
),
2064
+
[RTD1625_ISO_EJTAG_VE2_LOC] = RTK_PIN_MUX(ejtag_ve2_loc, 0x120, GENMASK(22, 20),
2065
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ve2_ejtag_loc0"),
2066
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ve2_ejtag_loc1"),
2067
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve2_ejtag_loc2")
2068
+
),
2069
+
[RTD1625_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
2070
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
2071
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
2072
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")
2073
+
),
2074
+
[RTD1625_ISO_EJTAG_PCPU_LOC] = RTK_PIN_MUX(ejtag_pcpu_loc, 0x120, GENMASK(28, 26),
2075
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "pcpu_ejtag_loc0"),
2076
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "pcpu_ejtag_loc1"),
2077
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 26), "pcpu_ejtag_loc2")
2078
+
),
2079
+
[RTD1625_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(31, 29),
2080
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "acpu_ejtag_loc0"),
2081
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "acpu_ejtag_loc1"),
2082
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 29), "acpu_ejtag_loc2")
2083
+
),
2084
+
[RTD1625_ISO_I2C6_LOC] = RTK_PIN_MUX(i2c6_loc, 0x128, GENMASK(1, 0),
2085
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c6_loc0"),
2086
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c6_loc1")
2087
+
),
2088
+
[RTD1625_ISO_UART0_LOC] = RTK_PIN_MUX(uart0_loc, 0x128, GENMASK(3, 2),
2089
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart0_loc0"),
2090
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "uart0_loc1")
2091
+
),
2092
+
[RTD1625_ISO_AI_I2S1_LOC] = RTK_PIN_MUX(ai_i2s1_loc, 0x128, GENMASK(5, 4),
2093
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_i2s1_loc0"),
2094
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_i2s1_loc1")
2095
+
),
2096
+
[RTD1625_ISO_AO_I2S1_LOC] = RTK_PIN_MUX(ao_i2s1_loc, 0x128, GENMASK(7, 6),
2097
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ao_i2s1_loc0"),
2098
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "ao_i2s1_loc1")
2099
+
),
2100
+
[RTD1625_ISO_ETN_PHY_LOC] = RTK_PIN_MUX(etn_phy_loc, 0x128, GENMASK(9, 8),
2101
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_phy_loc0"),
2102
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "etn_phy_loc1")
2103
+
),
2104
+
[RTD1625_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(14, 13),
2105
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "spdif_loc0"),
2106
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "spdif_loc1")
2107
+
),
2108
+
[RTD1625_ISO_RGMII_VDSEL] = RTK_PIN_MUX(rgmii_vdsel, 0x188, GENMASK(17, 16),
2109
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "rgmii_3v3"),
2110
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "rgmii_2v5"),
2111
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rgmii_1v8"),
2112
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii_1v2")
2113
+
),
2114
+
[RTD1625_ISO_CSI_VDSEL] = RTK_PIN_MUX(csi_vdsel, 0x188, GENMASK(19, 18),
2115
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "csi_3v3"),
2116
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "csi_2v5"),
2117
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "csi_1v8"),
2118
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "csi_1v2")
2119
+
),
2120
+
2121
+
[RTD1625_ISO_SPDIF_IN_MODE] = RTK_PIN_MUX(spdif_in_mode, 0x188, GENMASK(20, 20),
2122
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "spdif_in_gpio"),
2123
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "spdif_in_coaxial")
2124
+
),
2125
+
};
2126
+
2127
+
static const struct rtd_pin_desc rtd1625_isom_muxes[] = {
2128
+
[RTD1625_ISOM_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x0, GENMASK(3, 0),
2129
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2130
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pctrl"),
2131
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2132
+
),
2133
+
[RTD1625_ISOM_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x0, GENMASK(7, 4),
2134
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2135
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "pctrl"),
2136
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "ir_rx_loc1"),
2137
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2138
+
),
2139
+
[RTD1625_ISOM_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x0, GENMASK(11, 8),
2140
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2141
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart10"),
2142
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pctrl"),
2143
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "isom_dbg_out"),
2144
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2145
+
),
2146
+
[RTD1625_ISOM_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x0, GENMASK(15, 12),
2147
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2148
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart10"),
2149
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pctrl"),
2150
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "ir_rx_loc0"),
2151
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "isom_dbg_out"),
2152
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2153
+
),
2154
+
[RTD1625_ISOM_IR_RX_LOC] = RTK_PIN_MUX(ir_rx_loc, 0x30, GENMASK(1, 0),
2155
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ir_rx_loc0"),
2156
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ir_rx_loc1")
2157
+
),
2158
+
};
2159
+
2160
+
static const struct rtd_pin_desc rtd1625_ve4_muxes[] = {
2161
+
[RTD1625_VE4_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x0, GENMASK(3, 0),
2162
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2163
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart0_loc0"),
2164
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2165
+
),
2166
+
[RTD1625_VE4_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x0, GENMASK(7, 4),
2167
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2168
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "uart0_loc0"),
2169
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2170
+
),
2171
+
[RTD1625_VE4_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x0, GENMASK(11, 8),
2172
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2173
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2"),
2174
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "gspi0"),
2175
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc0"),
2176
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc0"),
2177
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc0"),
2178
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc0"),
2179
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc0"),
2180
+
RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "gpu_ejtag_loc0"),
2181
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc0"),
2182
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2183
+
),
2184
+
[RTD1625_VE4_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x0, GENMASK(15, 12),
2185
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2186
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2"),
2187
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "gspi0"),
2188
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc0"),
2189
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc0"),
2190
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc0"),
2191
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aucpu0_ejtag_loc0"),
2192
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc0"),
2193
+
RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "gpu_ejtag_loc0"),
2194
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aucpu1_ejtag_loc0"),
2195
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2196
+
),
2197
+
[RTD1625_VE4_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x0, GENMASK(20, 16),
2198
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2199
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2"),
2200
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "gspi0"),
2201
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc0"),
2202
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc0"),
2203
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc0"),
2204
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aucpu0_ejtag_loc0"),
2205
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc0"),
2206
+
RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "gpu_ejtag_loc0"),
2207
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm0_loc1"),
2208
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aucpu1_ejtag_loc0"),
2209
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2210
+
),
2211
+
[RTD1625_VE4_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x0, GENMASK(24, 21),
2212
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
2213
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2"),
2214
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "gspi0"),
2215
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "scpu_ejtag_loc0"),
2216
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "acpu_ejtag_loc0"),
2217
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "pcpu_ejtag_loc0"),
2218
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 21), "aucpu0_ejtag_loc0"),
2219
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 21), "ve2_ejtag_loc0"),
2220
+
RTK_PIN_FUNC(SHIFT_LEFT(0xc, 21), "gpu_ejtag_loc0"),
2221
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 21), "pwm1_loc0"),
2222
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 21), "aucpu1_ejtag_loc0"),
2223
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate")
2224
+
),
2225
+
[RTD1625_VE4_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x0, GENMASK(28, 25),
2226
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
2227
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "i2c0"),
2228
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 25), "pwm0_loc3"),
2229
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate")
2230
+
),
2231
+
2232
+
[RTD1625_VE4_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x4, GENMASK(3, 0),
2233
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2234
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c0"),
2235
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2236
+
),
2237
+
[RTD1625_VE4_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x4, GENMASK(7, 4),
2238
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2239
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "dptx_hpd"),
2240
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "pwm2_loc0"),
2241
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2242
+
),
2243
+
[RTD1625_VE4_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x4, GENMASK(11, 8),
2244
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2245
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2246
+
),
2247
+
[RTD1625_VE4_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x4, GENMASK(15, 12),
2248
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2249
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "pcie0"),
2250
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2251
+
),
2252
+
[RTD1625_VE4_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x4, GENMASK(19, 16),
2253
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2254
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm3_loc0"),
2255
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2256
+
),
2257
+
[RTD1625_VE4_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x4, GENMASK(23, 20),
2258
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2259
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2260
+
),
2261
+
[RTD1625_VE4_GPIO_24] = RTK_PIN_MUX(gpio_24, 0x4, GENMASK(27, 24),
2262
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2263
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c3"),
2264
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2265
+
),
2266
+
[RTD1625_VE4_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x4, GENMASK(31, 28),
2267
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2268
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c3"),
2269
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2270
+
),
2271
+
2272
+
[RTD1625_VE4_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x8, GENMASK(3, 0),
2273
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2274
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pcie1"),
2275
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2276
+
),
2277
+
[RTD1625_VE4_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x8, GENMASK(7, 4),
2278
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2279
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2280
+
),
2281
+
[RTD1625_VE4_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x8, GENMASK(11, 8),
2282
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2283
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart9"),
2284
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc2"),
2285
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2286
+
),
2287
+
[RTD1625_VE4_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x8, GENMASK(15, 12),
2288
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2289
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart9"),
2290
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc2"),
2291
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2292
+
),
2293
+
[RTD1625_VE4_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x8, GENMASK(19, 16),
2294
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2295
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2296
+
),
2297
+
[RTD1625_VE4_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x8, GENMASK(23, 20),
2298
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2299
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2300
+
),
2301
+
[RTD1625_VE4_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x8, GENMASK(27, 24),
2302
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2303
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
2304
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2305
+
),
2306
+
[RTD1625_VE4_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x8, GENMASK(31, 28),
2307
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2308
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
2309
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2310
+
),
2311
+
2312
+
[RTD1625_VE4_GPIO_44] = RTK_PIN_MUX(gpio_44, 0xc, GENMASK(3, 0),
2313
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2314
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2315
+
),
2316
+
[RTD1625_VE4_GPIO_51] = RTK_PIN_MUX(gpio_51, 0xc, GENMASK(7, 4),
2317
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2318
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c6_loc1"),
2319
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2320
+
),
2321
+
[RTD1625_VE4_GPIO_53] = RTK_PIN_MUX(gpio_53, 0xc, GENMASK(11, 8),
2322
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2323
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart3"),
2324
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts0"),
2325
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi2"),
2326
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc0"),
2327
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2328
+
),
2329
+
[RTD1625_VE4_GPIO_54] = RTK_PIN_MUX(gpio_54, 0xc, GENMASK(15, 12),
2330
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2331
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart3"),
2332
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts0"),
2333
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi2"),
2334
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc0"),
2335
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2336
+
),
2337
+
[RTD1625_VE4_GPIO_55] = RTK_PIN_MUX(gpio_55, 0xc, GENMASK(19, 16),
2338
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2339
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart3"),
2340
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ts0"),
2341
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi2"),
2342
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2343
+
),
2344
+
[RTD1625_VE4_GPIO_56] = RTK_PIN_MUX(gpio_56, 0xc, GENMASK(23, 20),
2345
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2346
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart3"),
2347
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ts0"),
2348
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "gspi2"),
2349
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2350
+
),
2351
+
[RTD1625_VE4_GPIO_57] = RTK_PIN_MUX(gpio_57, 0xc, GENMASK(27, 24),
2352
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2353
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart5"),
2354
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "uart0_loc1"),
2355
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "gspi1"),
2356
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2357
+
),
2358
+
[RTD1625_VE4_GPIO_58] = RTK_PIN_MUX(gpio_58, 0xc, GENMASK(31, 28),
2359
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2360
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart5"),
2361
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "uart0_loc1"),
2362
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi1"),
2363
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2364
+
),
2365
+
2366
+
[RTD1625_VE4_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x10, GENMASK(3, 0),
2367
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2368
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart4"),
2369
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c4"),
2370
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi1"),
2371
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2372
+
),
2373
+
[RTD1625_VE4_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x10, GENMASK(7, 4),
2374
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2375
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart4"),
2376
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c4"),
2377
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi1"),
2378
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2379
+
),
2380
+
[RTD1625_VE4_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x10, GENMASK(11, 8),
2381
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2382
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c6_loc1"),
2383
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "spdif_out"),
2384
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spdif_in_optical"),
2385
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2386
+
),
2387
+
[RTD1625_VE4_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x10, GENMASK(15, 12),
2388
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2389
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pll_test_loc0"),
2390
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2391
+
),
2392
+
[RTD1625_VE4_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x10, GENMASK(19, 16),
2393
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2394
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"),
2395
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2396
+
),
2397
+
[RTD1625_VE4_GPIO_92] = RTK_PIN_MUX(gpio_92, 0x10, GENMASK(23, 20),
2398
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2399
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart6"),
2400
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c7"),
2401
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve4_uart_loc1"),
2402
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2403
+
),
2404
+
[RTD1625_VE4_GPIO_93] = RTK_PIN_MUX(gpio_93, 0x10, GENMASK(27, 24),
2405
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2406
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart6"),
2407
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c7"),
2408
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "ve4_uart_loc1"),
2409
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm1_loc1"),
2410
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2411
+
),
2412
+
[RTD1625_VE4_GPIO_132] = RTK_PIN_MUX(gpio_132, 0x10, GENMASK(31, 28),
2413
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2414
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm6"),
2415
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2416
+
),
2417
+
2418
+
[RTD1625_VE4_GPIO_133] = RTK_PIN_MUX(gpio_133, 0x14, GENMASK(3, 0),
2419
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2420
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ts1"),
2421
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2422
+
),
2423
+
[RTD1625_VE4_GPIO_134] = RTK_PIN_MUX(gpio_134, 0x14, GENMASK(7, 4),
2424
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2425
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ts1"),
2426
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2427
+
),
2428
+
[RTD1625_VE4_GPIO_135] = RTK_PIN_MUX(gpio_135, 0x14, GENMASK(11, 8),
2429
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2430
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts1"),
2431
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2432
+
),
2433
+
[RTD1625_VE4_GPIO_136] = RTK_PIN_MUX(gpio_136, 0x14, GENMASK(15, 12),
2434
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2435
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts1"),
2436
+
RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "pwm0_loc0"),
2437
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2438
+
),
2439
+
[RTD1625_VE4_GPIO_137] = RTK_PIN_MUX(gpio_137, 0x14, GENMASK(19, 16),
2440
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2441
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "i2c6_loc0"),
2442
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2443
+
),
2444
+
[RTD1625_VE4_GPIO_138] = RTK_PIN_MUX(gpio_138, 0x14, GENMASK(23, 20),
2445
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2446
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c6_loc0"),
2447
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2448
+
),
2449
+
[RTD1625_VE4_GPIO_139] = RTK_PIN_MUX(gpio_139, 0x14, GENMASK(27, 24),
2450
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2451
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2452
+
),
2453
+
[RTD1625_VE4_GPIO_140] = RTK_PIN_MUX(gpio_140, 0x14, GENMASK(31, 28),
2454
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2455
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2456
+
),
2457
+
2458
+
[RTD1625_VE4_GPIO_141] = RTK_PIN_MUX(gpio_141, 0x18, GENMASK(3, 0),
2459
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2460
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "csi0"),
2461
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2462
+
),
2463
+
[RTD1625_VE4_GPIO_142] = RTK_PIN_MUX(gpio_142, 0x18, GENMASK(7, 4),
2464
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2465
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2466
+
),
2467
+
[RTD1625_VE4_GPIO_143] = RTK_PIN_MUX(gpio_143, 0x18, GENMASK(11, 8),
2468
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2469
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2470
+
),
2471
+
[RTD1625_VE4_GPIO_144] = RTK_PIN_MUX(gpio_144, 0x18, GENMASK(15, 12),
2472
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2473
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "csi1"),
2474
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2475
+
),
2476
+
[RTD1625_VE4_GPIO_164] = RTK_PIN_MUX(gpio_164, 0x18, GENMASK(19, 16),
2477
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2478
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc1"),
2479
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc1"),
2480
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "i2c5"),
2481
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2482
+
),
2483
+
[RTD1625_VE4_GPIO_165] = RTK_PIN_MUX(gpio_165, 0x18, GENMASK(23, 20),
2484
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2485
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc1"),
2486
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc1"),
2487
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "i2c5"),
2488
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2489
+
),
2490
+
[RTD1625_VE4_UART_LOC] = RTK_PIN_MUX(ve4_uart_loc, 0x80, GENMASK(2, 0),
2491
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ve4_uart_loc0"),
2492
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ve4_uart_loc1"),
2493
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ve4_uart_loc2")
2494
+
),
2495
+
};
2496
+
2497
+
static const struct rtd_pin_desc rtd1625_main2_muxes[] = {
2498
+
[RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
2499
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2500
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
2501
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2502
+
),
2503
+
[RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
2504
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2505
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
2506
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2507
+
),
2508
+
[RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
2509
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2510
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
2511
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2512
+
),
2513
+
[RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
2514
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2515
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
2516
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2517
+
),
2518
+
[RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
2519
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2520
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
2521
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf"),
2522
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2523
+
),
2524
+
[RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
2525
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2526
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
2527
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "nf"),
2528
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2529
+
),
2530
+
[RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
2531
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2532
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
2533
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "nf"),
2534
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2535
+
),
2536
+
[RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
2537
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2538
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
2539
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "nf"),
2540
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2541
+
),
2542
+
2543
+
[RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
2544
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2545
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
2546
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "nf"),
2547
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2548
+
),
2549
+
[RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
2550
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2551
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
2552
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "nf"),
2553
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2554
+
),
2555
+
[RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
2556
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2557
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
2558
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2559
+
),
2560
+
[RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
2561
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2562
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
2563
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2564
+
),
2565
+
[RTD1625_MAIN2_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x4, GENMASK(19, 16),
2566
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2567
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc0"),
2568
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc0"),
2569
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
2570
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2571
+
),
2572
+
[RTD1625_MAIN2_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x4, GENMASK(23, 20),
2573
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2574
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc0"),
2575
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc0"),
2576
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
2577
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2578
+
),
2579
+
[RTD1625_MAIN2_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x4, GENMASK(27, 24),
2580
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2581
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c1"),
2582
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2583
+
),
2584
+
[RTD1625_MAIN2_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x4, GENMASK(31, 28),
2585
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2586
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c1"),
2587
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2588
+
),
2589
+
2590
+
[RTD1625_MAIN2_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(3, 0),
2591
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2592
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")
2593
+
),
2594
+
[RTD1625_MAIN2_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x8, GENMASK(7, 4),
2595
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2596
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
2597
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc1"),
2598
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc1"),
2599
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc1"),
2600
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aupu0_ejtag_loc1"),
2601
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc1"),
2602
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"),
2603
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"),
2604
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aupu1_ejtag_loc1"),
2605
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2606
+
),
2607
+
[RTD1625_MAIN2_HIF_EN] = RTK_PIN_MUX(hif_en, 0x8, GENMASK(11, 8),
2608
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2609
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
2610
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc1"),
2611
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc1"),
2612
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc1"),
2613
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aupu0_ejtag_loc1"),
2614
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc1"),
2615
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"),
2616
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"),
2617
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aupu1_ejtag_loc1"),
2618
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2619
+
),
2620
+
[RTD1625_MAIN2_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x8, GENMASK(15, 12),
2621
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2622
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
2623
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc1"),
2624
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc1"),
2625
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc1"),
2626
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aupu0_ejtag_loc1"),
2627
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc1"),
2628
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"),
2629
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"),
2630
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aupu1_ejtag_loc1"),
2631
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2632
+
),
2633
+
[RTD1625_MAIN2_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x8, GENMASK(19, 16),
2634
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2635
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
2636
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc1"),
2637
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc1"),
2638
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc1"),
2639
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aupu0_ejtag_loc1"),
2640
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc1"),
2641
+
RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
2642
+
RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
2643
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aupu1_ejtag_loc1"),
2644
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2645
+
),
2646
+
[RTD1625_MAIN2_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x8, GENMASK(23, 20),
2647
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2648
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
2649
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "scpu_ejtag_loc1"),
2650
+
RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "acpu_ejtag_loc1"),
2651
+
RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "pcpu_ejtag_loc1"),
2652
+
RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "aupu0_ejtag_loc1"),
2653
+
RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "ve2_ejtag_loc1"),
2654
+
RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "aupu1_ejtag_loc1"),
2655
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2656
+
),
2657
+
[RTD1625_MAIN2_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x8, GENMASK(27, 24),
2658
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2659
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
2660
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2661
+
),
2662
+
[RTD1625_MAIN2_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x8, GENMASK(31, 28),
2663
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2664
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi"),
2665
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2666
+
),
2667
+
2668
+
[RTD1625_MAIN2_GPIO_65] = RTK_PIN_MUX(gpio_65, 0xc, GENMASK(3, 0),
2669
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2670
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
2671
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "spi"),
2672
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2673
+
),
2674
+
[RTD1625_MAIN2_GPIO_66] = RTK_PIN_MUX(gpio_66, 0xc, GENMASK(7, 4),
2675
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2676
+
RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"),
2677
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "spi"),
2678
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2679
+
),
2680
+
[RTD1625_MAIN2_GPIO_67] = RTK_PIN_MUX(gpio_67, 0xc, GENMASK(13, 8),
2681
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2682
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "spi"),
2683
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2684
+
),
2685
+
[RTD1625_MAIN2_GPIO_80] = RTK_PIN_MUX(gpio_80, 0xc, GENMASK(15, 12),
2686
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2687
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"),
2688
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"),
2689
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2690
+
),
2691
+
[RTD1625_MAIN2_GPIO_81] = RTK_PIN_MUX(gpio_81, 0xc, GENMASK(19, 16),
2692
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2693
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"),
2694
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
2695
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2696
+
),
2697
+
[RTD1625_MAIN2_GPIO_82] = RTK_PIN_MUX(gpio_82, 0xc, GENMASK(23, 20),
2698
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2699
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "rmii"),
2700
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
2701
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2702
+
),
2703
+
[RTD1625_MAIN2_GPIO_83] = RTK_PIN_MUX(gpio_83, 0xc, GENMASK(27, 24),
2704
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2705
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "rmii"),
2706
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"),
2707
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2708
+
),
2709
+
[RTD1625_MAIN2_GPIO_84] = RTK_PIN_MUX(gpio_84, 0xc, GENMASK(31, 28),
2710
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
2711
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "rmii"),
2712
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "rgmii"),
2713
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
2714
+
),
2715
+
2716
+
[RTD1625_MAIN2_GPIO_85] = RTK_PIN_MUX(gpio_85, 0x10, GENMASK(3, 0),
2717
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
2718
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "rgmii"),
2719
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
2720
+
),
2721
+
[RTD1625_MAIN2_GPIO_86] = RTK_PIN_MUX(gpio_86, 0x10, GENMASK(7, 4),
2722
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
2723
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "rgmii"),
2724
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
2725
+
),
2726
+
[RTD1625_MAIN2_GPIO_87] = RTK_PIN_MUX(gpio_87, 0x10, GENMASK(11, 8),
2727
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
2728
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "rmii"),
2729
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "rgmii"),
2730
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
2731
+
),
2732
+
[RTD1625_MAIN2_GPIO_88] = RTK_PIN_MUX(gpio_88, 0x10, GENMASK(15, 12),
2733
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
2734
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"),
2735
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"),
2736
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
2737
+
),
2738
+
[RTD1625_MAIN2_GPIO_89] = RTK_PIN_MUX(gpio_89, 0x10, GENMASK(19, 16),
2739
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
2740
+
RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"),
2741
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
2742
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
2743
+
),
2744
+
[RTD1625_MAIN2_GPIO_90] = RTK_PIN_MUX(gpio_90, 0x10, GENMASK(23, 20),
2745
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
2746
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
2747
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
2748
+
),
2749
+
[RTD1625_MAIN2_GPIO_91] = RTK_PIN_MUX(gpio_91, 0x10, GENMASK(27, 24),
2750
+
RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
2751
+
RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"),
2752
+
RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
2753
+
),
2754
+
};
2755
+
2756
+
static const struct rtd_pin_config_desc rtd1625_iso_configs[] = {
2757
+
[RTD1625_ISO_GPIO_8] = RTK_PIN_CONFIG_V2(gpio_8, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2758
+
[RTD1625_ISO_GPIO_9] = RTK_PIN_CONFIG_V2(gpio_9, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2759
+
[RTD1625_ISO_GPIO_10] = RTK_PIN_CONFIG_V2(gpio_10, 0x20, 12, 1, 2, 0, 3, 4, 5,
2760
+
PADDRI_4_8),
2761
+
[RTD1625_ISO_GPIO_11] = RTK_PIN_CONFIG_V2(gpio_11, 0x20, 18, 1, 2, 0, 3, 4, 5,
2762
+
PADDRI_4_8),
2763
+
[RTD1625_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x24, 0, 0, 1, NA, 2, 12, NA),
2764
+
[RTD1625_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x24, 13, 0, 1, NA, 2, 12, NA),
2765
+
[RTD1625_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x28, 0, 0, 1, NA, 2, 12, NA),
2766
+
[RTD1625_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x28, 13, 0, 1, NA, 2, 12, NA),
2767
+
[RTD1625_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x2c, 0, 0, 1, NA, 2, 12, NA),
2768
+
[RTD1625_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x2c, 13, 0, 1, NA, 2, 12, NA),
2769
+
[RTD1625_ISO_GPIO_52] = RTK_PIN_CONFIG_V2(gpio_52, 0x2c, 26, 1, 2, 0, 3, 4, 5,
2770
+
PADDRI_4_8),
2771
+
[RTD1625_ISO_GPIO_94] = RTK_PIN_CONFIG_V2(gpio_94, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2772
+
[RTD1625_ISO_GPIO_95] = RTK_PIN_CONFIG_V2(gpio_95, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2773
+
[RTD1625_ISO_GPIO_96] = RTK_PIN_CONFIG_V2(gpio_96, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2774
+
[RTD1625_ISO_GPIO_97] = RTK_PIN_CONFIG_V2(gpio_97, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2775
+
[RTD1625_ISO_GPIO_98] = RTK_PIN_CONFIG_V2(gpio_98, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2776
+
[RTD1625_ISO_GPIO_99] = RTK_PIN_CONFIG_V2(gpio_99, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2777
+
[RTD1625_ISO_GPIO_100] = RTK_PIN_CONFIG_V2(gpio_100, 0x34, 6, 1, 2, 0, 3, 4, 5,
2778
+
PADDRI_4_8),
2779
+
[RTD1625_ISO_GPIO_101] = RTK_PIN_CONFIG_V2(gpio_101, 0x34, 12, 1, 2, 0, 3, 4, 5,
2780
+
PADDRI_4_8),
2781
+
[RTD1625_ISO_GPIO_102] = RTK_PIN_CONFIG_V2(gpio_102, 0x34, 18, 1, 2, 0, 3, 4, 5,
2782
+
PADDRI_4_8),
2783
+
[RTD1625_ISO_GPIO_103] = RTK_PIN_CONFIG_V2(gpio_103, 0x34, 24, 1, 2, 0, 3, 4, 5,
2784
+
PADDRI_4_8),
2785
+
[RTD1625_ISO_GPIO_104] = RTK_PIN_CONFIG_V2(gpio_104, 0x38, 0, 1, 2, 0, 3, 4, 5,
2786
+
PADDRI_4_8),
2787
+
[RTD1625_ISO_GPIO_105] = RTK_PIN_CONFIG_V2(gpio_105, 0x38, 6, 1, 2, 0, 3, 4, 5,
2788
+
PADDRI_4_8),
2789
+
[RTD1625_ISO_GPIO_106] = RTK_PIN_CONFIG_V2(gpio_106, 0x38, 12, 1, 2, 0, 3, 4, 5,
2790
+
PADDRI_4_8),
2791
+
[RTD1625_ISO_GPIO_107] = RTK_PIN_CONFIG_V2(gpio_107, 0x38, 18, 1, 2, 0, 3, 4, 5,
2792
+
PADDRI_4_8),
2793
+
[RTD1625_ISO_GPIO_108] = RTK_PIN_CONFIG_V2(gpio_108, 0x38, 24, 1, 2, 0, 3, 4, 5,
2794
+
PADDRI_4_8),
2795
+
[RTD1625_ISO_GPIO_109] = RTK_PIN_CONFIG_V2(gpio_109, 0x3c, 0, 1, 2, 0, 3, 4, 5,
2796
+
PADDRI_4_8),
2797
+
[RTD1625_ISO_GPIO_110] = RTK_PIN_CONFIG_V2(gpio_110, 0x3c, 6, 1, 2, 0, 3, 4, 5,
2798
+
PADDRI_4_8),
2799
+
[RTD1625_ISO_GPIO_111] = RTK_PIN_CONFIG_V2(gpio_111, 0x3c, 12, 1, 2, 0, 3, 4, 5,
2800
+
PADDRI_4_8),
2801
+
[RTD1625_ISO_GPIO_112] = RTK_PIN_CONFIG_V2(gpio_112, 0x3c, 18, 1, 2, 0, 3, 4, 5,
2802
+
PADDRI_4_8),
2803
+
[RTD1625_ISO_GPIO_128] = RTK_PIN_CONFIG_V2(gpio_128, 0x3c, 24, 1, 2, 0, 3, 4, 5,
2804
+
PADDRI_4_8),
2805
+
[RTD1625_ISO_GPIO_129] = RTK_PIN_CONFIG_V2(gpio_129, 0x40, 0, 1, 2, 0, 3, 4, 5,
2806
+
PADDRI_4_8),
2807
+
[RTD1625_ISO_GPIO_130] = RTK_PIN_CONFIG_V2(gpio_130, 0x40, 6, 1, 2, 0, 3, 4, 5,
2808
+
PADDRI_4_8),
2809
+
[RTD1625_ISO_GPIO_131] = RTK_PIN_CONFIG_V2(gpio_131, 0x40, 12, 1, 2, 0, 3, 4, 5,
2810
+
PADDRI_4_8),
2811
+
[RTD1625_ISO_GPIO_145] = RTK_PIN_CONFIG_V2(gpio_145, 0x40, 18, 1, 2, 0, 3, 4, 5,
2812
+
PADDRI_4_8),
2813
+
[RTD1625_ISO_GPIO_146] = RTK_PIN_CONFIG_V2(gpio_146, 0x40, 24, 1, 2, 0, 3, 4, 5,
2814
+
PADDRI_4_8),
2815
+
[RTD1625_ISO_GPIO_147] = RTK_PIN_CONFIG_V2(gpio_147, 0x44, 0, 1, 2, 0, 3, 4, 5,
2816
+
PADDRI_4_8),
2817
+
[RTD1625_ISO_GPIO_148] = RTK_PIN_CONFIG_V2(gpio_148, 0x44, 6, 1, 2, 0, 3, 4, 5,
2818
+
PADDRI_4_8),
2819
+
[RTD1625_ISO_GPIO_149] = RTK_PIN_CONFIG_V2(gpio_149, 0x44, 12, 1, 2, 0, 3, 4, 5,
2820
+
PADDRI_4_8),
2821
+
[RTD1625_ISO_GPIO_150] = RTK_PIN_CONFIG_V2(gpio_150, 0x44, 18, 1, 2, 0, 3, 4, 5,
2822
+
PADDRI_4_8),
2823
+
[RTD1625_ISO_GPIO_151] = RTK_PIN_CONFIG_V2(gpio_151, 0x44, 24, 1, 2, 0, 3, 4, 5,
2824
+
PADDRI_4_8),
2825
+
[RTD1625_ISO_GPIO_152] = RTK_PIN_CONFIG_V2(gpio_152, 0x48, 0, 1, 2, 0, 3, 4, 5,
2826
+
PADDRI_4_8),
2827
+
[RTD1625_ISO_GPIO_153] = RTK_PIN_CONFIG_V2(gpio_153, 0x48, 6, 1, 2, 0, 3, 4, 5,
2828
+
PADDRI_4_8),
2829
+
[RTD1625_ISO_GPIO_154] = RTK_PIN_CONFIG_V2(gpio_154, 0x48, 12, 1, 2, 0, 3, 4, 5,
2830
+
PADDRI_4_8),
2831
+
[RTD1625_ISO_GPIO_155] = RTK_PIN_CONFIG_V2(gpio_155, 0x48, 18, 1, 2, 0, 3, 4, 5,
2832
+
PADDRI_4_8),
2833
+
[RTD1625_ISO_GPIO_156] = RTK_PIN_CONFIG_V2(gpio_156, 0x48, 24, 1, 2, 0, 3, 4, 5,
2834
+
PADDRI_4_8),
2835
+
[RTD1625_ISO_GPIO_157] = RTK_PIN_CONFIG_V2(gpio_157, 0x4c, 0, 1, 2, 0, 3, 4, 5,
2836
+
PADDRI_4_8),
2837
+
[RTD1625_ISO_GPIO_158] = RTK_PIN_CONFIG_V2(gpio_158, 0x4c, 6, 1, 2, 0, 3, 4, 5,
2838
+
PADDRI_4_8),
2839
+
[RTD1625_ISO_GPIO_159] = RTK_PIN_CONFIG_V2(gpio_159, 0x4c, 12, 1, 2, 0, 3, 4, 5,
2840
+
PADDRI_4_8),
2841
+
[RTD1625_ISO_GPIO_160] = RTK_PIN_CONFIG_V2(gpio_160, 0x4c, 18, 1, 2, 0, 3, 4, 5,
2842
+
PADDRI_4_8),
2843
+
[RTD1625_ISO_GPIO_161] = RTK_PIN_CONFIG_V2(gpio_161, 0x4c, 24, 1, 2, 0, 3, 4, 5,
2844
+
PADDRI_4_8),
2845
+
[RTD1625_ISO_GPIO_162] = RTK_PIN_CONFIG_V2(gpio_162, 0x50, 0, 1, 2, 0, 3, 4, 5,
2846
+
PADDRI_4_8),
2847
+
[RTD1625_ISO_GPIO_163] = RTK_PIN_CONFIG_V2(gpio_163, 0x50, 6, 1, 2, 0, 3, 4, 5,
2848
+
PADDRI_4_8),
2849
+
[RTD1625_ISO_USB_CC1] = RTK_PIN_CONFIG_V2(usb_cc1, 0x50, 12, NA, NA, 0, 1, 2, 3,
2850
+
PADDRI_4_8),
2851
+
[RTD1625_ISO_USB_CC2] = RTK_PIN_CONFIG_V2(usb_cc2, 0x50, 16, NA, NA, 0, 1, 2, 3,
2852
+
PADDRI_4_8),
2853
+
};
2854
+
2855
+
static const struct rtd_pin_config_desc rtd1625_isom_configs[] = {
2856
+
[RTD1625_ISOM_GPIO_0] = RTK_PIN_CONFIG_V2(gpio_0, 0x4, 5, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2857
+
[RTD1625_ISOM_GPIO_1] = RTK_PIN_CONFIG_V2(gpio_1, 0x4, 11, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2858
+
[RTD1625_ISOM_GPIO_28] = RTK_PIN_CONFIG_V2(gpio_28, 0x4, 17, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2859
+
[RTD1625_ISOM_GPIO_29] = RTK_PIN_CONFIG_V2(gpio_29, 0x4, 23, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2860
+
};
2861
+
2862
+
static const struct rtd_pin_config_desc rtd1625_ve4_configs[] = {
2863
+
[RTD1625_VE4_GPIO_2] = RTK_PIN_CONFIG_V2(gpio_2, 0x1c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2864
+
[RTD1625_VE4_GPIO_3] = RTK_PIN_CONFIG_V2(gpio_3, 0x1c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2865
+
[RTD1625_VE4_GPIO_4] = RTK_PIN_CONFIG_V2(gpio_4, 0x1c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2866
+
[RTD1625_VE4_GPIO_5] = RTK_PIN_CONFIG_V2(gpio_5, 0x1c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2867
+
[RTD1625_VE4_GPIO_6] = RTK_PIN_CONFIG_V2(gpio_6, 0x1c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2868
+
[RTD1625_VE4_GPIO_7] = RTK_PIN_CONFIG_V2(gpio_7, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2869
+
[RTD1625_VE4_GPIO_12] = RTK_PIN_CONFIG_V2(gpio_12, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2870
+
[RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2871
+
[RTD1625_VE4_GPIO_16] = RTK_PIN_CONFIG_V2(gpio_16, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2872
+
[RTD1625_VE4_GPIO_17] = RTK_PIN_CONFIG_V2(gpio_17, 0x20, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2873
+
[RTD1625_VE4_GPIO_18] = RTK_PIN_CONFIG_V2(gpio_18, 0x24, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2874
+
[RTD1625_VE4_GPIO_19] = RTK_PIN_CONFIG_V2(gpio_19, 0x24, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2875
+
[RTD1625_VE4_GPIO_23] = RTK_PIN_CONFIG_V2(gpio_23, 0x24, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2876
+
[RTD1625_VE4_GPIO_24] = RTK_PIN_CONFIG_V2(gpio_24, 0x24, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2877
+
[RTD1625_VE4_GPIO_25] = RTK_PIN_CONFIG_V2(gpio_25, 0x24, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2878
+
[RTD1625_VE4_GPIO_30] = RTK_PIN_CONFIG_V2(gpio_30, 0x28, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2879
+
[RTD1625_VE4_GPIO_31] = RTK_PIN_CONFIG_V2(gpio_31, 0x28, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2880
+
[RTD1625_VE4_GPIO_32] = RTK_PIN_CONFIG_V2(gpio_32, 0x28, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2881
+
[RTD1625_VE4_GPIO_33] = RTK_PIN_CONFIG_V2(gpio_33, 0x28, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2882
+
[RTD1625_VE4_GPIO_34] = RTK_PIN_CONFIG_V2(gpio_34, 0x28, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2883
+
[RTD1625_VE4_GPIO_35] = RTK_PIN_CONFIG_V2(gpio_35, 0x2c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2884
+
[RTD1625_VE4_GPIO_42] = RTK_PIN_CONFIG_V2(gpio_42, 0x2c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2885
+
[RTD1625_VE4_GPIO_43] = RTK_PIN_CONFIG_V2(gpio_43, 0x2c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2886
+
[RTD1625_VE4_GPIO_44] = RTK_PIN_CONFIG_V2(gpio_44, 0x2c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2887
+
[RTD1625_VE4_GPIO_51] = RTK_PIN_CONFIG_V2(gpio_51, 0x2c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2888
+
[RTD1625_VE4_GPIO_53] = RTK_PIN_CONFIG_V2(gpio_53, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2889
+
[RTD1625_VE4_GPIO_54] = RTK_PIN_CONFIG_V2(gpio_54, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2890
+
[RTD1625_VE4_GPIO_55] = RTK_PIN_CONFIG_V2(gpio_55, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2891
+
[RTD1625_VE4_GPIO_56] = RTK_PIN_CONFIG_V2(gpio_56, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2892
+
[RTD1625_VE4_GPIO_57] = RTK_PIN_CONFIG_V2(gpio_57, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2893
+
[RTD1625_VE4_GPIO_58] = RTK_PIN_CONFIG_V2(gpio_58, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2894
+
[RTD1625_VE4_GPIO_59] = RTK_PIN_CONFIG_V2(gpio_59, 0x34, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2895
+
[RTD1625_VE4_GPIO_60] = RTK_PIN_CONFIG_V2(gpio_60, 0x34, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2896
+
[RTD1625_VE4_GPIO_61] = RTK_PIN_CONFIG_V2(gpio_61, 0x34, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2897
+
[RTD1625_VE4_GPIO_62] = RTK_PIN_CONFIG_V2(gpio_62, 0x34, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2898
+
[RTD1625_VE4_GPIO_63] = RTK_PIN_CONFIG_V2(gpio_63, 0x38, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2899
+
[RTD1625_VE4_GPIO_92] = RTK_PIN_CONFIG_V2(gpio_92, 0x38, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2900
+
[RTD1625_VE4_GPIO_93] = RTK_PIN_CONFIG_V2(gpio_93, 0x38, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
2901
+
[RTD1625_VE4_GPIO_132] = RTK_PIN_CONFIG_V2(gpio_132, 0x38, 18, 1, 2, 0, 3, 4, 5,
2902
+
PADDRI_4_8),
2903
+
[RTD1625_VE4_GPIO_133] = RTK_PIN_CONFIG_V2(gpio_133, 0x38, 24, 1, 2, 0, 3, 4, 5,
2904
+
PADDRI_4_8),
2905
+
[RTD1625_VE4_GPIO_134] = RTK_PIN_CONFIG_V2(gpio_134, 0x3c, 0, 1, 2, 0, 3, 4, 5,
2906
+
PADDRI_4_8),
2907
+
[RTD1625_VE4_GPIO_135] = RTK_PIN_CONFIG_V2(gpio_135, 0x3c, 6, 1, 2, 0, 3, 4, 5,
2908
+
PADDRI_4_8),
2909
+
[RTD1625_VE4_GPIO_136] = RTK_PIN_CONFIG_V2(gpio_136, 0x3c, 12, 1, 2, 0, 3, 4, 5,
2910
+
PADDRI_4_8),
2911
+
[RTD1625_VE4_GPIO_137] = RTK_PIN_CONFIG(gpio_137, 0x3c, 18, 1, 2, 0, NA, NA, PADDRI_4_8),
2912
+
[RTD1625_VE4_GPIO_138] = RTK_PIN_CONFIG(gpio_138, 0x3c, 21, 1, 2, 0, NA, NA, PADDRI_4_8),
2913
+
[RTD1625_VE4_GPIO_139] = RTK_PIN_CONFIG(gpio_139, 0x3c, 24, 1, 2, 0, NA, NA, PADDRI_4_8),
2914
+
[RTD1625_VE4_GPIO_140] = RTK_PIN_CONFIG(gpio_140, 0x3c, 27, 1, 2, 0, NA, NA, PADDRI_4_8),
2915
+
[RTD1625_VE4_GPIO_141] = RTK_PIN_CONFIG(gpio_141, 0x40, 0, 1, 2, 0, NA, NA, PADDRI_4_8),
2916
+
[RTD1625_VE4_GPIO_142] = RTK_PIN_CONFIG(gpio_142, 0x40, 3, 1, 2, 0, NA, NA, PADDRI_4_8),
2917
+
[RTD1625_VE4_GPIO_143] = RTK_PIN_CONFIG(gpio_143, 0x40, 6, 1, 2, 0, NA, NA, PADDRI_4_8),
2918
+
[RTD1625_VE4_GPIO_144] = RTK_PIN_CONFIG(gpio_144, 0x40, 9, 1, 2, 0, NA, NA, PADDRI_4_8),
2919
+
[RTD1625_VE4_GPIO_164] = RTK_PIN_CONFIG(gpio_164, 0x40, 12, 1, 2, 0, NA, NA, PADDRI_4_8),
2920
+
[RTD1625_VE4_GPIO_165] = RTK_PIN_CONFIG(gpio_165, 0x40, 15, 1, 2, 0, NA, NA, PADDRI_4_8),
2921
+
};
2922
+
2923
+
static const struct rtd_pin_config_desc rtd1625_main2_configs[] = {
2924
+
[RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x14, 0, 0, 1, NA, 2, 12, NA),
2925
+
[RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x14, 13, 0, 1, NA, 2, 13, NA),
2926
+
[RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x18, 0, 0, 1, NA, 2, 12, NA),
2927
+
[RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x18, 13, 0, 1, NA, 2, 12, NA),
2928
+
[RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x1c, 0, 0, 1, NA, 2, 12, NA),
2929
+
[RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x1c, 13, 0, 1, NA, 2, 12, NA),
2930
+
[RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x20, 0, 0, 1, NA, 2, 12, NA),
2931
+
[RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x20, 13, 0, 1, NA, 2, 12, NA),
2932
+
[RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x24, 0, 0, 1, NA, 2, 12, NA),
2933
+
[RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x24, 13, 0, 1, NA, 2, 12, NA),
2934
+
[RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x28, 0, 0, 1, NA, 2, 12, NA),
2935
+
[RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x28, 13, 0, 1, NA, 2, 12, NA),
2936
+
[RTD1625_MAIN2_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x28, 26, 1, 2, 0, NA, NA, PADDRI_4_8),
2937
+
[RTD1625_MAIN2_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x28, 29, 1, 2, 0, NA, NA, PADDRI_4_8),
2938
+
[RTD1625_MAIN2_GPIO_20] = RTK_PIN_CONFIG_I2C(gpio_20, 0x2c, 0, 1, 2, 0, 3, 4, 5, 7, 8,
2939
+
PADDRI_4_8),
2940
+
[RTD1625_MAIN2_GPIO_21] = RTK_PIN_CONFIG_I2C(gpio_21, 0x2c, 9, 1, 2, 0, 3, 4, 5, 7, 8,
2941
+
PADDRI_4_8),
2942
+
[RTD1625_MAIN2_GPIO_22] = RTK_PIN_CONFIG_V2(gpio_22, 0x2c, 18, 1, 2, 0, 3, 7, 8,
2943
+
PADDRI_4_8),
2944
+
[RTD1625_MAIN2_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x30, 0, 0, 1, NA, 2, 12, NA),
2945
+
[RTD1625_MAIN2_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x30, 13, 0, 1, NA, 2, 12, NA),
2946
+
[RTD1625_MAIN2_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x34, 0, 0, 1, NA, 2, 12, NA),
2947
+
[RTD1625_MAIN2_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x34, 13, 0, 1, NA, 2, 12, NA),
2948
+
[RTD1625_MAIN2_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x38, 0, 0, 1, NA, 2, 12, NA),
2949
+
[RTD1625_MAIN2_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x38, 13, 0, 1, NA, 2, 12, NA),
2950
+
[RTD1625_MAIN2_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x38, 26, 1, 2, 0, NA, NA, PADDRI_4_8),
2951
+
[RTD1625_MAIN2_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x38, 29, 1, 2, 0, NA, NA, PADDRI_4_8),
2952
+
[RTD1625_MAIN2_GPIO_82] = RTK_PIN_CONFIG(gpio_82, 0x3c, 0, 1, 2, 0, NA, NA, PADDRI_4_8),
2953
+
[RTD1625_MAIN2_GPIO_83] = RTK_PIN_CONFIG(gpio_83, 0x3c, 3, 1, 2, 0, NA, NA, PADDRI_4_8),
2954
+
[RTD1625_MAIN2_GPIO_84] = RTK_PIN_CONFIG(gpio_84, 0x3c, 6, 1, 2, 0, NA, NA, PADDRI_4_8),
2955
+
[RTD1625_MAIN2_GPIO_85] = RTK_PIN_CONFIG(gpio_85, 0x3c, 9, 1, 2, NA, NA, NA, PADDRI_4_8),
2956
+
[RTD1625_MAIN2_GPIO_86] = RTK_PIN_CONFIG(gpio_86, 0x3c, 12, 1, 2, NA, NA, NA, PADDRI_4_8),
2957
+
[RTD1625_MAIN2_GPIO_87] = RTK_PIN_CONFIG(gpio_87, 0x3c, 22, 1, 2, NA, NA, NA, PADDRI_4_8),
2958
+
[RTD1625_MAIN2_GPIO_88] = RTK_PIN_CONFIG(gpio_88, 0x40, 0, 1, 2, NA, NA, NA, PADDRI_4_8),
2959
+
[RTD1625_MAIN2_GPIO_89] = RTK_PIN_CONFIG(gpio_89, 0x40, 10, 1, 2, NA, NA, NA, PADDRI_4_8),
2960
+
[RTD1625_MAIN2_GPIO_90] = RTK_PIN_CONFIG(gpio_90, 0x40, 20, 1, 2, NA, NA, NA, PADDRI_4_8),
2961
+
[RTD1625_MAIN2_GPIO_91] = RTK_PIN_CONFIG(gpio_91, 0x44, 0, 1, 2, NA, NA, NA, PADDRI_4_8),
2962
+
[RTD1625_MAIN2_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x44, 10, 0, 1, NA, 2, 12, NA),
2963
+
[RTD1625_MAIN2_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x48, 0, 0, 1, NA, 2, 12, NA),
2964
+
[RTD1625_MAIN2_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x48, 13, 0, 1, NA, 2, 12, NA),
2965
+
[RTD1625_MAIN2_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x4c, 0, 0, 1, NA, 2, 12, NA),
2966
+
};
2967
+
2968
+
static const struct rtd_pin_sconfig_desc rtd1625_iso_sconfigs[] = {
2969
+
RTK_PIN_SCONFIG(gpio_45, 0x24, 3, 3, 6, 3, 9, 3),
2970
+
RTK_PIN_SCONFIG(gpio_46, 0x24, 16, 3, 19, 3, 22, 3),
2971
+
RTK_PIN_SCONFIG(gpio_47, 0x28, 3, 3, 6, 3, 9, 3),
2972
+
RTK_PIN_SCONFIG(gpio_48, 0x28, 16, 3, 19, 3, 22, 3),
2973
+
RTK_PIN_SCONFIG(gpio_49, 0x2c, 3, 3, 6, 3, 9, 3),
2974
+
RTK_PIN_SCONFIG(gpio_50, 0x2c, 16, 3, 19, 3, 22, 3),
2975
+
};
2976
+
2977
+
static const struct rtd_pin_sconfig_desc rtd1625_main2_sconfigs[] = {
2978
+
RTK_PIN_SCONFIG(emmc_clk, 0x14, 3, 3, 6, 3, 9, 3),
2979
+
RTK_PIN_SCONFIG(emmc_cmd, 0x14, 16, 3, 19, 3, 22, 3),
2980
+
RTK_PIN_SCONFIG(emmc_data_0, 0x18, 3, 3, 6, 3, 9, 3),
2981
+
RTK_PIN_SCONFIG(emmc_data_1, 0x18, 16, 3, 19, 3, 22, 3),
2982
+
RTK_PIN_SCONFIG(emmc_data_2, 0x1c, 3, 3, 6, 3, 9, 3),
2983
+
RTK_PIN_SCONFIG(emmc_data_3, 0x1c, 16, 3, 19, 3, 22, 3),
2984
+
RTK_PIN_SCONFIG(emmc_data_4, 0x20, 3, 3, 6, 3, 9, 3),
2985
+
RTK_PIN_SCONFIG(emmc_data_5, 0x20, 16, 3, 19, 3, 22, 3),
2986
+
RTK_PIN_SCONFIG(emmc_data_6, 0x24, 3, 3, 6, 3, 9, 3),
2987
+
RTK_PIN_SCONFIG(emmc_data_7, 0x24, 16, 3, 19, 3, 22, 3),
2988
+
RTK_PIN_SCONFIG(emmc_dd_sb, 0x28, 3, 3, 6, 3, 9, 3),
2989
+
RTK_PIN_SCONFIG(emmc_rst_n, 0x28, 16, 3, 19, 3, 22, 3),
2990
+
RTK_PIN_SCONFIG(gpio_40, 0x30, 3, 3, 6, 3, 9, 3),
2991
+
RTK_PIN_SCONFIG(gpio_41, 0x30, 16, 3, 19, 3, 22, 3),
2992
+
RTK_PIN_SCONFIG(gpio_64, 0x34, 3, 3, 6, 3, 9, 3),
2993
+
RTK_PIN_SCONFIG(gpio_65, 0x34, 16, 3, 19, 3, 22, 3),
2994
+
RTK_PIN_SCONFIG(gpio_66, 0x38, 3, 3, 6, 3, 9, 3),
2995
+
RTK_PIN_SCONFIG(gpio_67, 0x38, 16, 3, 19, 3, 22, 3),
2996
+
RTK_PIN_SCONFIG(gpio_86, 0x3c, 0, 0, 14, 4, 18, 4),
2997
+
RTK_PIN_SCONFIG(gpio_87, 0x3c, 0, 0, 24, 4, 28, 4),
2998
+
RTK_PIN_SCONFIG(gpio_88, 0x40, 0, 0, 2, 4, 6, 4),
2999
+
RTK_PIN_SCONFIG(gpio_89, 0x40, 0, 0, 12, 4, 16, 4),
3000
+
RTK_PIN_SCONFIG(gpio_90, 0x40, 0, 0, 22, 4, 26, 4),
3001
+
RTK_PIN_SCONFIG(gpio_91, 0x44, 0, 0, 2, 4, 6, 4),
3002
+
RTK_PIN_SCONFIG(hif_clk, 0x44, 13, 3, 16, 3, 19, 3),
3003
+
RTK_PIN_SCONFIG(hif_data, 0x48, 3, 3, 6, 3, 9, 3),
3004
+
RTK_PIN_SCONFIG(hif_en, 0x48, 16, 3, 19, 3, 22, 3),
3005
+
RTK_PIN_SCONFIG(hif_rdy, 0x4c, 3, 3, 6, 3, 9, 3),
3006
+
};
3007
+
3008
+
static const struct rtd_reg_range rtd1625_iso_reg_ranges[] = {
3009
+
{ .offset = 0x0, .len = 0x58 },
3010
+
{ .offset = 0x120, .len = 0x10 },
3011
+
{ .offset = 0x180, .len = 0xc },
3012
+
{ .offset = 0x1A0, .len = 0xc },
3013
+
};
3014
+
3015
+
static const struct rtd_pin_range rtd1625_iso_pin_ranges = {
3016
+
.ranges = rtd1625_iso_reg_ranges,
3017
+
.num_ranges = ARRAY_SIZE(rtd1625_iso_reg_ranges),
3018
+
};
3019
+
3020
+
static const struct rtd_reg_range rtd1625_isom_reg_ranges[] = {
3021
+
{ .offset = 0x0, .len = 0xc },
3022
+
{ .offset = 0x30, .len = 0x4 },
3023
+
};
3024
+
3025
+
static const struct rtd_pin_range rtd1625_isom_pin_ranges = {
3026
+
.ranges = rtd1625_isom_reg_ranges,
3027
+
.num_ranges = ARRAY_SIZE(rtd1625_isom_reg_ranges),
3028
+
};
3029
+
3030
+
static const struct rtd_reg_range rtd1625_ve4_reg_ranges[] = {
3031
+
{ .offset = 0x0, .len = 0x48 },
3032
+
{ .offset = 0x80, .len = 0x4 },
3033
+
};
3034
+
3035
+
static const struct rtd_pin_range rtd1625_ve4_pin_ranges = {
3036
+
.ranges = rtd1625_ve4_reg_ranges,
3037
+
.num_ranges = ARRAY_SIZE(rtd1625_ve4_reg_ranges),
3038
+
};
3039
+
3040
+
static const struct rtd_reg_range rtd1625_main2_reg_ranges[] = {
3041
+
{ .offset = 0x0, .len = 0x50 },
3042
+
};
3043
+
3044
+
static const struct rtd_pin_range rtd1625_main2_pin_ranges = {
3045
+
.ranges = rtd1625_main2_reg_ranges,
3046
+
.num_ranges = ARRAY_SIZE(rtd1625_main2_reg_ranges),
3047
+
};
3048
+
3049
+
static const struct rtd_pinctrl_desc rtd1625_iso_pinctrl_desc = {
3050
+
.pins = rtd1625_iso_pins,
3051
+
.num_pins = ARRAY_SIZE(rtd1625_iso_pins),
3052
+
.groups = rtd1625_iso_pin_groups,
3053
+
.num_groups = ARRAY_SIZE(rtd1625_iso_pin_groups),
3054
+
.functions = rtd1625_iso_pin_functions,
3055
+
.num_functions = ARRAY_SIZE(rtd1625_iso_pin_functions),
3056
+
.muxes = rtd1625_iso_muxes,
3057
+
.num_muxes = ARRAY_SIZE(rtd1625_iso_muxes),
3058
+
.configs = rtd1625_iso_configs,
3059
+
.num_configs = ARRAY_SIZE(rtd1625_iso_configs),
3060
+
.sconfigs = rtd1625_iso_sconfigs,
3061
+
.num_sconfigs = ARRAY_SIZE(rtd1625_iso_sconfigs),
3062
+
.pin_range = &rtd1625_iso_pin_ranges,
3063
+
};
3064
+
3065
+
static const struct rtd_pinctrl_desc rtd1625_isom_pinctrl_desc = {
3066
+
.pins = rtd1625_isom_pins,
3067
+
.num_pins = ARRAY_SIZE(rtd1625_isom_pins),
3068
+
.groups = rtd1625_isom_pin_groups,
3069
+
.num_groups = ARRAY_SIZE(rtd1625_isom_pin_groups),
3070
+
.functions = rtd1625_isom_pin_functions,
3071
+
.num_functions = ARRAY_SIZE(rtd1625_isom_pin_functions),
3072
+
.muxes = rtd1625_isom_muxes,
3073
+
.num_muxes = ARRAY_SIZE(rtd1625_isom_muxes),
3074
+
.configs = rtd1625_isom_configs,
3075
+
.num_configs = ARRAY_SIZE(rtd1625_isom_configs),
3076
+
.pin_range = &rtd1625_isom_pin_ranges,
3077
+
};
3078
+
3079
+
static const struct rtd_pinctrl_desc rtd1625_ve4_pinctrl_desc = {
3080
+
.pins = rtd1625_ve4_pins,
3081
+
.num_pins = ARRAY_SIZE(rtd1625_ve4_pins),
3082
+
.groups = rtd1625_ve4_pin_groups,
3083
+
.num_groups = ARRAY_SIZE(rtd1625_ve4_pin_groups),
3084
+
.functions = rtd1625_ve4_pin_functions,
3085
+
.num_functions = ARRAY_SIZE(rtd1625_ve4_pin_functions),
3086
+
.muxes = rtd1625_ve4_muxes,
3087
+
.num_muxes = ARRAY_SIZE(rtd1625_ve4_muxes),
3088
+
.configs = rtd1625_ve4_configs,
3089
+
.num_configs = ARRAY_SIZE(rtd1625_ve4_configs),
3090
+
.pin_range = &rtd1625_ve4_pin_ranges,
3091
+
};
3092
+
3093
+
static const struct rtd_pinctrl_desc rtd1625_main2_pinctrl_desc = {
3094
+
.pins = rtd1625_main2_pins,
3095
+
.num_pins = ARRAY_SIZE(rtd1625_main2_pins),
3096
+
.groups = rtd1625_main2_pin_groups,
3097
+
.num_groups = ARRAY_SIZE(rtd1625_main2_pin_groups),
3098
+
.functions = rtd1625_main2_pin_functions,
3099
+
.num_functions = ARRAY_SIZE(rtd1625_main2_pin_functions),
3100
+
.muxes = rtd1625_main2_muxes,
3101
+
.num_muxes = ARRAY_SIZE(rtd1625_main2_muxes),
3102
+
.configs = rtd1625_main2_configs,
3103
+
.num_configs = ARRAY_SIZE(rtd1625_main2_configs),
3104
+
.sconfigs = rtd1625_main2_sconfigs,
3105
+
.num_sconfigs = ARRAY_SIZE(rtd1625_main2_sconfigs),
3106
+
.pin_range = &rtd1625_main2_pin_ranges,
3107
+
};
3108
+
3109
+
static int rtd1625_pinctrl_probe(struct platform_device *pdev)
3110
+
{
3111
+
const struct rtd_pinctrl_desc *desc = device_get_match_data(&pdev->dev);
3112
+
3113
+
return rtd_pinctrl_probe(pdev, desc);
3114
+
}
3115
+
3116
+
static const struct of_device_id rtd1625_pinctrl_of_match[] = {
3117
+
{.compatible = "realtek,rtd1625-iso-pinctrl", .data = &rtd1625_iso_pinctrl_desc},
3118
+
{.compatible = "realtek,rtd1625-isom-pinctrl", .data = &rtd1625_isom_pinctrl_desc},
3119
+
{.compatible = "realtek,rtd1625-ve4-pinctrl", .data = &rtd1625_ve4_pinctrl_desc},
3120
+
{.compatible = "realtek,rtd1625-main2-pinctrl", .data = &rtd1625_main2_pinctrl_desc},
3121
+
{},
3122
+
};
3123
+
MODULE_DEVICE_TABLE(of, rtd1625_pinctrl_of_match);
3124
+
3125
+
static struct platform_driver rtd1625_pinctrl_driver = {
3126
+
.driver = {
3127
+
.name = "rtd1625-pinctrl",
3128
+
.of_match_table = rtd1625_pinctrl_of_match,
3129
+
.pm = &realtek_pinctrl_pm_ops,
3130
+
},
3131
+
.probe = rtd1625_pinctrl_probe,
3132
+
};
3133
+
3134
+
module_platform_driver(rtd1625_pinctrl_driver);
3135
+
3136
+
MODULE_LICENSE("GPL");
3137
+
MODULE_AUTHOR("Realtek Semiconductor Corporation");
3138
+
MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 pinctrl driver");
+7
-1
drivers/pinctrl/renesas/pinctrl-rzg2l.c
+7
-1
drivers/pinctrl/renesas/pinctrl-rzg2l.c
···
1475
1475
arg = pinconf_to_config_argument(_configs[i]);
1476
1476
switch (param) {
1477
1477
case PIN_CONFIG_INPUT_ENABLE:
1478
-
1479
1478
if (!(cfg & PIN_CFG_IEN))
1480
1479
return -EINVAL;
1481
1480
···
3010
3011
cfg = pctrl->data->port_pin_configs[port];
3011
3012
off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3012
3013
pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));
3014
+
3015
+
if (cfg & RZG2L_VARIABLE_CFG) {
3016
+
unsigned int pin = port * RZG2L_PINS_PER_PORT;
3017
+
3018
+
for (unsigned int i = 0; i < RZG2L_PINS_PER_PORT; i++)
3019
+
cfg |= *(u64 *)pctrl->desc.pins[pin + i].drv_data;
3020
+
}
3013
3021
3014
3022
caps = FIELD_GET(PIN_CFG_MASK, cfg);
3015
3023
has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
+258
drivers/pinctrl/renesas/pinctrl-rzt2h.c
+258
drivers/pinctrl/renesas/pinctrl-rzt2h.c
···
7
7
* Copyright (C) 2025 Renesas Electronics Corporation.
8
8
*/
9
9
10
+
#include <linux/array_size.h>
10
11
#include <linux/bitfield.h>
11
12
#include <linux/bitops.h>
12
13
#include <linux/bits.h>
···
44
43
#define PMC(m) (0x400 + (m))
45
44
#define PFC(m) (0x600 + 8 * (m))
46
45
#define PIN(m) (0x800 + (m))
46
+
#define DRCTL(n) (0xa00 + 8 * (n))
47
47
#define RSELP(m) (0xc00 + (m))
48
48
49
49
#define PM_MASK GENMASK(1, 0)
···
55
53
#define PFC_MASK GENMASK_ULL(5, 0)
56
54
#define PFC_PIN_MASK(pin) (PFC_MASK << ((pin) * 8))
57
55
#define PFC_FUNC_INTERRUPT 0
56
+
57
+
#define DRCTL_DRV_PIN_MASK(pin) (GENMASK_ULL(1, 0) << ((pin) * 8))
58
+
#define DRCTL_PUD_PIN_MASK(pin) (GENMASK_ULL(3, 2) << ((pin) * 8))
59
+
#define DRCTL_SMT_PIN_MASK(pin) (BIT_ULL(4) << ((pin) * 8))
60
+
#define DRCTL_SR_PIN_MASK(pin) (BIT_ULL(5) << ((pin) * 8))
61
+
62
+
#define DRCTL_PUD_NONE 0
63
+
#define DRCTL_PUD_PULL_UP 1
64
+
#define DRCTL_PUD_PULL_DOWN 2
58
65
59
66
/*
60
67
* Use 16 lower bits [15:0] for pin identifier
···
102
91
atomic_t wakeup_path;
103
92
};
104
93
94
+
static const unsigned int rzt2h_drive_strength_ua[] = { 2500, 5000, 9000, 11800 };
95
+
105
96
#define RZT2H_GET_BASE(pctrl, port) \
106
97
((port) > RZT2H_MAX_SAFETY_PORTS ? (pctrl)->base0 : (pctrl)->base1)
107
98
···
122
109
RZT2H_PINCTRL_REG_ACCESS(b, u8)
123
110
RZT2H_PINCTRL_REG_ACCESS(w, u16)
124
111
RZT2H_PINCTRL_REG_ACCESS(q, u64)
112
+
113
+
static int rzt2h_drive_strength_ua_to_idx(unsigned int ua)
114
+
{
115
+
unsigned int i;
116
+
117
+
for (i = 0; i < ARRAY_SIZE(rzt2h_drive_strength_ua); i++) {
118
+
if (rzt2h_drive_strength_ua[i] == ua)
119
+
return i;
120
+
}
121
+
122
+
return -EINVAL;
123
+
}
124
+
125
+
static int rzt2h_drive_strength_idx_to_ua(unsigned int idx)
126
+
{
127
+
if (idx >= ARRAY_SIZE(rzt2h_drive_strength_ua))
128
+
return -EINVAL;
129
+
130
+
return rzt2h_drive_strength_ua[idx];
131
+
}
132
+
133
+
static void rzt2h_pinctrl_drctl_rmwq(struct rzt2h_pinctrl *pctrl,
134
+
u32 port, u64 mask, u64 val)
135
+
{
136
+
u32 offset = DRCTL(port);
137
+
u64 drctl;
138
+
139
+
guard(raw_spinlock_irqsave)(&pctrl->lock);
140
+
drctl = rzt2h_pinctrl_readq(pctrl, port, offset) & ~mask;
141
+
rzt2h_pinctrl_writeq(pctrl, port, drctl | val, offset);
142
+
}
125
143
126
144
static int rzt2h_validate_pin(struct rzt2h_pinctrl *pctrl, unsigned int offset)
127
145
{
···
487
443
return ret;
488
444
}
489
445
446
+
static int rzt2h_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
447
+
unsigned int pin,
448
+
unsigned long *config)
449
+
{
450
+
struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
451
+
u32 port, param = pinconf_to_config_param(*config);
452
+
unsigned int arg;
453
+
u8 port_pin;
454
+
u64 drctl;
455
+
int ret;
456
+
457
+
ret = rzt2h_validate_pin(pctrl, pin);
458
+
if (ret)
459
+
return ret;
460
+
461
+
port = RZT2H_PIN_ID_TO_PORT(pin);
462
+
port_pin = RZT2H_PIN_ID_TO_PIN(pin);
463
+
464
+
switch (param) {
465
+
case PIN_CONFIG_SLEW_RATE:
466
+
drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
467
+
arg = field_get(DRCTL_SR_PIN_MASK(port_pin), drctl);
468
+
break;
469
+
470
+
case PIN_CONFIG_BIAS_DISABLE:
471
+
case PIN_CONFIG_BIAS_PULL_UP:
472
+
case PIN_CONFIG_BIAS_PULL_DOWN:
473
+
drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
474
+
arg = field_get(DRCTL_PUD_PIN_MASK(port_pin), drctl);
475
+
/* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
476
+
switch (arg) {
477
+
case DRCTL_PUD_NONE:
478
+
if (param != PIN_CONFIG_BIAS_DISABLE)
479
+
return -EINVAL;
480
+
break;
481
+
case DRCTL_PUD_PULL_UP:
482
+
if (param != PIN_CONFIG_BIAS_PULL_UP)
483
+
return -EINVAL;
484
+
arg = 1;
485
+
break;
486
+
case DRCTL_PUD_PULL_DOWN:
487
+
if (param != PIN_CONFIG_BIAS_PULL_DOWN)
488
+
return -EINVAL;
489
+
arg = 1;
490
+
break;
491
+
default:
492
+
return -EINVAL;
493
+
}
494
+
break;
495
+
496
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
497
+
drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
498
+
arg = field_get(DRCTL_SMT_PIN_MASK(port_pin), drctl);
499
+
if (!arg)
500
+
return -EINVAL;
501
+
break;
502
+
503
+
case PIN_CONFIG_DRIVE_STRENGTH_UA: {
504
+
int idx_drv;
505
+
506
+
drctl = rzt2h_pinctrl_readq(pctrl, port, DRCTL(port));
507
+
arg = field_get(DRCTL_DRV_PIN_MASK(port_pin), drctl);
508
+
idx_drv = rzt2h_drive_strength_idx_to_ua(arg);
509
+
if (idx_drv < 0)
510
+
return idx_drv;
511
+
arg = idx_drv;
512
+
break;
513
+
}
514
+
515
+
default:
516
+
return -ENOTSUPP;
517
+
}
518
+
519
+
*config = pinconf_to_config_packed(param, arg);
520
+
return 0;
521
+
}
522
+
523
+
static int rzt2h_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
524
+
unsigned int pin,
525
+
unsigned long *configs,
526
+
unsigned int num_configs)
527
+
{
528
+
struct rzt2h_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
529
+
unsigned int i;
530
+
u8 port_pin;
531
+
int ret;
532
+
533
+
ret = rzt2h_validate_pin(pctrl, pin);
534
+
if (ret)
535
+
return ret;
536
+
537
+
port_pin = RZT2H_PIN_ID_TO_PIN(pin);
538
+
539
+
for (i = 0; i < num_configs; i++) {
540
+
u32 arg = pinconf_to_config_argument(configs[i]);
541
+
u32 param = pinconf_to_config_param(configs[i]);
542
+
u64 mask, val;
543
+
544
+
switch (param) {
545
+
case PIN_CONFIG_SLEW_RATE:
546
+
mask = DRCTL_SR_PIN_MASK(port_pin);
547
+
val = field_prep(mask, !!arg);
548
+
break;
549
+
550
+
case PIN_CONFIG_BIAS_DISABLE:
551
+
case PIN_CONFIG_BIAS_PULL_UP:
552
+
case PIN_CONFIG_BIAS_PULL_DOWN: {
553
+
u32 bias;
554
+
555
+
switch (param) {
556
+
case PIN_CONFIG_BIAS_DISABLE:
557
+
bias = DRCTL_PUD_NONE;
558
+
break;
559
+
case PIN_CONFIG_BIAS_PULL_UP:
560
+
bias = DRCTL_PUD_PULL_UP;
561
+
break;
562
+
case PIN_CONFIG_BIAS_PULL_DOWN:
563
+
bias = DRCTL_PUD_PULL_DOWN;
564
+
break;
565
+
}
566
+
567
+
mask = DRCTL_PUD_PIN_MASK(port_pin);
568
+
val = field_prep(mask, bias);
569
+
break;
570
+
}
571
+
572
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
573
+
mask = DRCTL_SMT_PIN_MASK(port_pin);
574
+
val = field_prep(mask, !!arg);
575
+
break;
576
+
577
+
case PIN_CONFIG_DRIVE_STRENGTH_UA: {
578
+
int drv_idx;
579
+
580
+
drv_idx = rzt2h_drive_strength_ua_to_idx(arg);
581
+
if (drv_idx < 0)
582
+
return drv_idx;
583
+
584
+
mask = DRCTL_DRV_PIN_MASK(port_pin);
585
+
val = field_prep(mask, drv_idx);
586
+
break;
587
+
}
588
+
589
+
default:
590
+
return -ENOTSUPP;
591
+
}
592
+
593
+
rzt2h_pinctrl_drctl_rmwq(pctrl, RZT2H_PIN_ID_TO_PORT(pin), mask, val);
594
+
}
595
+
596
+
return 0;
597
+
}
598
+
599
+
static int rzt2h_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
600
+
unsigned int group,
601
+
unsigned long *config)
602
+
{
603
+
unsigned long prev_config = 0;
604
+
const unsigned int *pins;
605
+
unsigned int i, npins;
606
+
int ret;
607
+
608
+
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
609
+
if (ret)
610
+
return ret;
611
+
612
+
for (i = 0; i < npins; i++) {
613
+
ret = rzt2h_pinctrl_pinconf_get(pctldev, pins[i], config);
614
+
if (ret)
615
+
return ret;
616
+
617
+
/* Check config matches previous pins */
618
+
if (i && prev_config != *config)
619
+
return -ENOTSUPP;
620
+
621
+
prev_config = *config;
622
+
}
623
+
624
+
return 0;
625
+
}
626
+
627
+
static int rzt2h_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
628
+
unsigned int group,
629
+
unsigned long *configs,
630
+
unsigned int num_configs)
631
+
{
632
+
const unsigned int *pins;
633
+
unsigned int i, npins;
634
+
int ret;
635
+
636
+
ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
637
+
if (ret)
638
+
return ret;
639
+
640
+
for (i = 0; i < npins; i++) {
641
+
ret = rzt2h_pinctrl_pinconf_set(pctldev, pins[i], configs,
642
+
num_configs);
643
+
if (ret)
644
+
return ret;
645
+
}
646
+
647
+
return 0;
648
+
}
649
+
490
650
static const struct pinctrl_ops rzt2h_pinctrl_pctlops = {
491
651
.get_groups_count = pinctrl_generic_get_group_count,
492
652
.get_group_name = pinctrl_generic_get_group_name,
···
705
457
.get_function_groups = pinmux_generic_get_function_groups,
706
458
.set_mux = rzt2h_pinctrl_set_mux,
707
459
.strict = true,
460
+
};
461
+
462
+
static const struct pinconf_ops rzt2h_pinctrl_confops = {
463
+
.is_generic = true,
464
+
.pin_config_get = rzt2h_pinctrl_pinconf_get,
465
+
.pin_config_set = rzt2h_pinctrl_pinconf_set,
466
+
.pin_config_group_set = rzt2h_pinctrl_pinconf_group_set,
467
+
.pin_config_group_get = rzt2h_pinctrl_pinconf_group_get,
468
+
.pin_config_config_dbg_show = pinconf_generic_dump_config,
708
469
};
709
470
710
471
static int rzt2h_gpio_request(struct gpio_chip *chip, unsigned int offset)
···
1147
890
desc->npins = pctrl->data->n_port_pins;
1148
891
desc->pctlops = &rzt2h_pinctrl_pctlops;
1149
892
desc->pmxops = &rzt2h_pinctrl_pmxops;
893
+
desc->confops = &rzt2h_pinctrl_confops;
1150
894
desc->owner = THIS_MODULE;
1151
895
1152
896
pins = devm_kcalloc(dev, desc->npins, sizeof(*pins), GFP_KERNEL);
+1
-1
drivers/pinctrl/sophgo/pinctrl-sg2042.c
+1
-1
drivers/pinctrl/sophgo/pinctrl-sg2042.c
+1
-1
drivers/pinctrl/sophgo/pinctrl-sg2044.c
+1
-1
drivers/pinctrl/sophgo/pinctrl-sg2044.c
+12
-9
drivers/pinctrl/spacemit/pinctrl-k1.c
+12
-9
drivers/pinctrl/spacemit/pinctrl-k1.c
···
674
674
arg = 0;
675
675
break;
676
676
default:
677
-
return -EINVAL;
677
+
return -ENOTSUPP;
678
678
}
679
679
680
680
*config = pinconf_to_config_packed(param, arg);
···
740
740
}
741
741
break;
742
742
default:
743
-
return -EINVAL;
743
+
return -ENOTSUPP;
744
744
}
745
745
}
746
746
···
814
814
struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
815
815
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
816
816
u32 value;
817
+
int ret;
817
818
818
-
if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
819
-
configs, num_configs, &value))
820
-
return -EINVAL;
819
+
ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
820
+
configs, num_configs, &value);
821
+
if (ret)
822
+
return ret;
821
823
822
824
return spacemit_pin_set_config(pctrl, pin, value);
823
825
}
···
833
831
const struct spacemit_pin *spin;
834
832
const struct group_desc *group;
835
833
u32 value;
836
-
int i;
834
+
int i, ret;
837
835
838
836
group = pinctrl_generic_get_group(pctldev, gsel);
839
837
if (!group)
840
838
return -EINVAL;
841
839
842
840
spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
843
-
if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
844
-
configs, num_configs, &value))
845
-
return -EINVAL;
841
+
ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
842
+
configs, num_configs, &value);
843
+
if (ret)
844
+
return ret;
846
845
847
846
for (i = 0; i < group->grp.npins; i++)
848
847
spacemit_pin_set_config(pctrl, group->grp.pins[i], value);
-2
drivers/pinctrl/starfive/Kconfig
-2
drivers/pinctrl/starfive/Kconfig
···
9
9
select GENERIC_PINCONF
10
10
select GPIOLIB
11
11
select GPIOLIB_IRQCHIP
12
-
select OF_GPIO
13
12
default SOC_STARFIVE
14
13
help
15
14
Say yes here to support pin control on the StarFive JH7100 SoC.
···
23
24
select GENERIC_PINCONF
24
25
select GPIOLIB
25
26
select GPIOLIB_IRQCHIP
26
-
select OF_GPIO
27
27
28
28
config PINCTRL_STARFIVE_JH7110_SYS
29
29
tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
-1
drivers/pinctrl/sunplus/Kconfig
-1
drivers/pinctrl/sunplus/Kconfig
+3
-7
drivers/pinctrl/tegra/pinctrl-tegra.c
+3
-7
drivers/pinctrl/tegra/pinctrl-tegra.c
···
832
832
int fn, gn, gfn;
833
833
unsigned long backup_regs_size = 0;
834
834
835
-
pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
835
+
pmx = devm_kzalloc(&pdev->dev,
836
+
struct_size(pmx, pingroup_configs, soc_data->ngroups), GFP_KERNEL);
836
837
if (!pmx)
837
838
return -ENOMEM;
838
839
839
840
pmx->dev = &pdev->dev;
840
841
pmx->soc = soc_data;
841
-
842
-
pmx->pingroup_configs = devm_kcalloc(&pdev->dev,
843
-
pmx->soc->ngroups, sizeof(*pmx->pingroup_configs),
844
-
GFP_KERNEL);
845
-
if (!pmx->pingroup_configs)
846
-
return -ENOMEM;
842
+
pmx->num_pingroup_configs = soc_data->ngroups;
847
843
848
844
/*
849
845
* Each mux group will appear in 4 functions' list of groups.
+2
-2
drivers/pinctrl/tegra/pinctrl-tegra.h
+2
-2
drivers/pinctrl/tegra/pinctrl-tegra.h
···
25
25
int nbanks;
26
26
void __iomem **regs;
27
27
u32 *backup_regs;
28
-
/* Array of size soc->ngroups */
29
-
struct tegra_pingroup_config *pingroup_configs;
28
+
unsigned int num_pingroup_configs;
29
+
struct tegra_pingroup_config pingroup_configs[] __counted_by(num_pingroup_configs);
30
30
};
31
31
32
32
enum tegra_pinconf_param {
+4
-1
include/linux/pinctrl/pinconf-generic.h
+4
-1
include/linux/pinctrl/pinconf-generic.h
···
83
83
* schmitt-trigger mode is disabled.
84
84
* @PIN_CONFIG_INPUT_SCHMITT_UV: this will configure an input pin to run in
85
85
* schmitt-trigger mode. The argument is in uV.
86
+
* @PIN_CONFIG_INPUT_VOLTAGE_UV: this will configure the input voltage level of
87
+
* the pin. The argument is specified in microvolts.
86
88
* @PIN_CONFIG_MODE_LOW_POWER: this will configure the pin for low power
87
89
* operation, if several modes of operation are supported these can be
88
90
* passed in the argument on a custom form, else just use argument 1
···
117
115
* @PIN_CONFIG_SKEW_DELAY_INPUT_PS: if the pin has independent values for the
118
116
* programmable skew rate (on inputs) and latch delay (on outputs), then
119
117
* this parameter specifies the clock skew only. The argument is in ps.
120
-
* @PIN_CONFIG_SKEW_DELAY_OUPUT_PS: if the pin has independent values for the
118
+
* @PIN_CONFIG_SKEW_DELAY_OUTPUT_PS: if the pin has independent values for the
121
119
* programmable skew rate (on inputs) and latch delay (on outputs), then
122
120
* this parameter specifies the latch delay only. The argument is in ps.
123
121
* @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state.
···
147
145
PIN_CONFIG_INPUT_SCHMITT,
148
146
PIN_CONFIG_INPUT_SCHMITT_ENABLE,
149
147
PIN_CONFIG_INPUT_SCHMITT_UV,
148
+
PIN_CONFIG_INPUT_VOLTAGE_UV,
150
149
PIN_CONFIG_MODE_LOW_POWER,
151
150
PIN_CONFIG_MODE_PWM,
152
151
PIN_CONFIG_LEVEL,