phy: qcom-qmp-usb: cleanup the driver · tjh.dev/kernel@faf83af

+11 -203

1 changed file

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drivers

phy

qualcomm

phy-qcom-qmp-usb.c

+11 -203

drivers/phy/qualcomm/phy-qcom-qmp-usb.c

··· 1359 1359 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1360 1360 const struct qmp_phy_init_tbl *serdes_tbl; 1361 1361 int serdes_tbl_num; 1362 - const struct qmp_phy_init_tbl *serdes_tbl_sec; 1363 - int serdes_tbl_num_sec; 1364 1362 const struct qmp_phy_init_tbl *tx_tbl; 1365 1363 int tx_tbl_num; 1366 - const struct qmp_phy_init_tbl *tx_tbl_sec; 1367 - int tx_tbl_num_sec; 1368 1364 const struct qmp_phy_init_tbl *rx_tbl; 1369 1365 int rx_tbl_num; 1370 - const struct qmp_phy_init_tbl *rx_tbl_sec; 1371 - int rx_tbl_num_sec; 1372 1366 const struct qmp_phy_init_tbl *pcs_tbl; 1373 1367 int pcs_tbl_num; 1374 - const struct qmp_phy_init_tbl *pcs_tbl_sec; 1375 - int pcs_tbl_num_sec; 1376 - const struct qmp_phy_init_tbl *pcs_misc_tbl; 1377 - int pcs_misc_tbl_num; 1378 - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; 1379 - int pcs_misc_tbl_num_sec; 1380 - 1381 - /* Init sequence for DP PHY block link rates */ 1382 - const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1383 - int serdes_tbl_rbr_num; 1384 - const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1385 - int serdes_tbl_hbr_num; 1386 - const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1387 - int serdes_tbl_hbr2_num; 1388 - const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1389 - int serdes_tbl_hbr3_num; 1390 - 1391 - /* DP PHY callbacks */ 1392 - int (*configure_dp_phy)(struct qmp_phy *qphy); 1393 - void (*configure_dp_tx)(struct qmp_phy *qphy); 1394 - int (*calibrate_dp_phy)(struct qmp_phy *qphy); 1395 - void (*dp_aux_init)(struct qmp_phy *qphy); 1396 1368 1397 1369 /* clock ids to be requested */ 1398 1370 const char * const *clk_list; ··· 1381 1409 1382 1410 unsigned int start_ctrl; 1383 1411 unsigned int pwrdn_ctrl; 1384 - unsigned int mask_com_pcs_ready; 1385 1412 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1386 1413 unsigned int phy_status; 1387 1414 1388 - /* true, if PHY has a separate PHY_COM control block */ 1389 - bool has_phy_com_ctrl; 1390 - /* true, if PHY has a reset for individual lanes */ 1391 - bool has_lane_rst; 1392 1415 /* true, if PHY needs delay after POWER_DOWN */ 1393 1416 bool has_pwrdn_delay; 1394 1417 /* power_down delay in usec */ ··· 1394 1427 bool has_phy_dp_com_ctrl; 1395 1428 /* true, if PHY has secondary tx/rx lanes to be configured */ 1396 1429 bool is_dual_lane_phy; 1397 - 1398 - /* true, if PCS block has no separate SW_RESET register */ 1399 - bool no_pcs_sw_reset; 1400 - }; 1401 - 1402 - struct qmp_phy_combo_cfg { 1403 - const struct qmp_phy_cfg *usb_cfg; 1404 - const struct qmp_phy_cfg *dp_cfg; 1405 1430 }; 1406 1431 1407 1432 /** ··· 1411 1452 * @pipe_clk: pipe clock 1412 1453 * @index: lane index 1413 1454 * @qmp: QMP phy to which this lane belongs 1414 - * @lane_rst: lane's reset controller 1415 1455 * @mode: current PHY mode 1416 - * @dp_aux_cfg: Display port aux config 1417 - * @dp_opts: Display port optional config 1418 - * @dp_clks: Display port clocks 1419 1456 */ 1420 1457 struct qmp_phy { 1421 1458 struct phy *phy; ··· 1426 1471 struct clk *pipe_clk; 1427 1472 unsigned int index; 1428 1473 struct qcom_qmp *qmp; 1429 - struct reset_control *lane_rst; 1430 1474 enum phy_mode mode; 1431 - unsigned int dp_aux_cfg; 1432 - struct phy_configure_opts_dp dp_opts; 1433 - struct qmp_phy_dp_clks *dp_clks; 1434 - }; 1435 - 1436 - struct qmp_phy_dp_clks { 1437 - struct qmp_phy *qphy; 1438 - struct clk_hw dp_link_hw; 1439 - struct clk_hw dp_pixel_hw; 1440 1475 }; 1441 1476 1442 1477 /** ··· 1442 1497 * @phys: array of per-lane phy descriptors 1443 1498 * @phy_mutex: mutex lock for PHY common block initialization 1444 1499 * @init_count: phy common block initialization count 1445 - * @ufs_reset: optional UFS PHY reset handle 1446 1500 */ 1447 1501 struct qcom_qmp { 1448 1502 struct device *dev; ··· 1455 1511 1456 1512 struct mutex phy_mutex; 1457 1513 int init_count; 1458 - 1459 - struct reset_control *ufs_reset; 1460 1514 }; 1461 1515 1462 1516 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) ··· 1998 2056 1999 2057 static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy) 2000 2058 { 2001 - struct qcom_qmp *qmp = qphy->qmp; 2002 2059 const struct qmp_phy_cfg *cfg = qphy->cfg; 2003 2060 void __iomem *serdes = qphy->serdes; 2004 2061 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 2005 2062 int serdes_tbl_num = cfg->serdes_tbl_num; 2006 - int ret; 2007 2063 2008 2064 qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); 2009 - if (cfg->serdes_tbl_sec) 2010 - qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec, 2011 - cfg->serdes_tbl_num_sec); 2012 - 2013 - if (cfg->has_phy_com_ctrl) { 2014 - void __iomem *status; 2015 - unsigned int mask, val; 2016 - 2017 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); 2018 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 2019 - SERDES_START | PCS_START); 2020 - 2021 - status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; 2022 - mask = cfg->mask_com_pcs_ready; 2023 - 2024 - ret = readl_poll_timeout(status, val, (val & mask), 10, 2025 - PHY_INIT_COMPLETE_TIMEOUT); 2026 - if (ret) { 2027 - dev_err(qmp->dev, 2028 - "phy common block init timed-out\n"); 2029 - return ret; 2030 - } 2031 - } 2032 2065 2033 2066 return 0; 2034 2067 } ··· 2012 2095 { 2013 2096 struct qcom_qmp *qmp = qphy->qmp; 2014 2097 const struct qmp_phy_cfg *cfg = qphy->cfg; 2015 - void __iomem *serdes = qphy->serdes; 2016 2098 void __iomem *pcs = qphy->pcs; 2017 2099 void __iomem *dp_com = qmp->dp_com; 2018 2100 int ret, i; ··· 2074 2158 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2075 2159 } 2076 2160 2077 - if (cfg->has_phy_com_ctrl) { 2078 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 2079 - SW_PWRDN); 2080 - } else { 2081 - if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2082 - qphy_setbits(pcs, 2083 - cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2084 - cfg->pwrdn_ctrl); 2085 - else 2086 - qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 2087 - cfg->pwrdn_ctrl); 2088 - } 2161 + if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2162 + qphy_setbits(pcs, 2163 + cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2164 + cfg->pwrdn_ctrl); 2165 + else 2166 + qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, 2167 + cfg->pwrdn_ctrl); 2089 2168 2090 2169 mutex_unlock(&qmp->phy_mutex); 2091 2170 ··· 2101 2190 { 2102 2191 struct qcom_qmp *qmp = qphy->qmp; 2103 2192 const struct qmp_phy_cfg *cfg = qphy->cfg; 2104 - void __iomem *serdes = qphy->serdes; 2105 2193 int i = cfg->num_resets; 2106 2194 2107 2195 mutex_lock(&qmp->phy_mutex); 2108 2196 if (--qmp->init_count) { 2109 2197 mutex_unlock(&qmp->phy_mutex); 2110 2198 return 0; 2111 - } 2112 - 2113 - reset_control_assert(qmp->ufs_reset); 2114 - if (cfg->has_phy_com_ctrl) { 2115 - qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], 2116 - SERDES_START | PCS_START); 2117 - qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], 2118 - SW_RESET); 2119 - qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], 2120 - SW_PWRDN); 2121 2199 } 2122 2200 2123 2201 while (--i >= 0) ··· 2125 2225 { 2126 2226 struct qmp_phy *qphy = phy_get_drvdata(phy); 2127 2227 struct qcom_qmp *qmp = qphy->qmp; 2128 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2129 2228 int ret; 2130 2229 dev_vdbg(qmp->dev, "Initializing QMP phy\n"); 2131 - 2132 - if (cfg->no_pcs_sw_reset) { 2133 - /* 2134 - * Get UFS reset, which is delayed until now to avoid a 2135 - * circular dependency where UFS needs its PHY, but the PHY 2136 - * needs this UFS reset. 2137 - */ 2138 - if (!qmp->ufs_reset) { 2139 - qmp->ufs_reset = 2140 - devm_reset_control_get_exclusive(qmp->dev, 2141 - "ufsphy"); 2142 - 2143 - if (IS_ERR(qmp->ufs_reset)) { 2144 - ret = PTR_ERR(qmp->ufs_reset); 2145 - dev_err(qmp->dev, 2146 - "failed to get UFS reset: %d\n", 2147 - ret); 2148 - 2149 - qmp->ufs_reset = NULL; 2150 - return ret; 2151 - } 2152 - } 2153 - 2154 - ret = reset_control_assert(qmp->ufs_reset); 2155 - if (ret) 2156 - return ret; 2157 - } 2158 2230 2159 2231 ret = qcom_qmp_phy_usb_com_init(qphy); 2160 2232 if (ret) ··· 2143 2271 void __iomem *tx = qphy->tx; 2144 2272 void __iomem *rx = qphy->rx; 2145 2273 void __iomem *pcs = qphy->pcs; 2146 - void __iomem *pcs_misc = qphy->pcs_misc; 2147 2274 void __iomem *status; 2148 2275 unsigned int mask, val, ready; 2149 2276 int ret; 2150 2277 2151 2278 qcom_qmp_phy_usb_serdes_init(qphy); 2152 2279 2153 - if (cfg->has_lane_rst) { 2154 - ret = reset_control_deassert(qphy->lane_rst); 2155 - if (ret) { 2156 - dev_err(qmp->dev, "lane%d reset deassert failed\n", 2157 - qphy->index); 2158 - return ret; 2159 - } 2160 - } 2161 - 2162 2280 ret = clk_prepare_enable(qphy->pipe_clk); 2163 2281 if (ret) { 2164 2282 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2165 - goto err_reset_lane; 2283 + return ret; 2166 2284 } 2167 2285 2168 2286 /* Tx, Rx, and PCS configurations */ 2169 2287 qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, 2170 2288 cfg->tx_tbl, cfg->tx_tbl_num, 1); 2171 - if (cfg->tx_tbl_sec) 2172 - qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, 2173 - cfg->tx_tbl_num_sec, 1); 2174 2289 2175 2290 /* Configuration for other LANE for USB-DP combo PHY */ 2176 2291 if (cfg->is_dual_lane_phy) { 2177 2292 qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, 2178 2293 cfg->tx_tbl, cfg->tx_tbl_num, 2); 2179 - if (cfg->tx_tbl_sec) 2180 - qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs, 2181 - cfg->tx_tbl_sec, 2182 - cfg->tx_tbl_num_sec, 2); 2183 2294 } 2184 2295 2185 2296 qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, 2186 2297 cfg->rx_tbl, cfg->rx_tbl_num, 1); 2187 - if (cfg->rx_tbl_sec) 2188 - qcom_qmp_phy_usb_configure_lane(rx, cfg->regs, 2189 - cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1); 2190 2298 2191 2299 if (cfg->is_dual_lane_phy) { 2192 2300 qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, 2193 2301 cfg->rx_tbl, cfg->rx_tbl_num, 2); 2194 - if (cfg->rx_tbl_sec) 2195 - qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs, 2196 - cfg->rx_tbl_sec, 2197 - cfg->rx_tbl_num_sec, 2); 2198 2302 } 2199 2303 2200 2304 /* Configure link rate, swing, etc. */ 2201 2305 qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2202 - if (cfg->pcs_tbl_sec) 2203 - qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, 2204 - cfg->pcs_tbl_num_sec); 2205 - 2206 - ret = reset_control_deassert(qmp->ufs_reset); 2207 - if (ret) 2208 - goto err_disable_pipe_clk; 2209 - 2210 - qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, 2211 - cfg->pcs_misc_tbl_num); 2212 - if (cfg->pcs_misc_tbl_sec) 2213 - qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec, 2214 - cfg->pcs_misc_tbl_num_sec); 2215 2306 2216 2307 if (cfg->has_pwrdn_delay) 2217 2308 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2218 2309 2219 2310 /* Pull PHY out of reset state */ 2220 - if (!cfg->no_pcs_sw_reset) 2221 - qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2311 + qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2312 + 2222 2313 /* start SerDes and Phy-Coding-Sublayer */ 2223 2314 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2224 2315 ··· 2200 2365 2201 2366 err_disable_pipe_clk: 2202 2367 clk_disable_unprepare(qphy->pipe_clk); 2203 - err_reset_lane: 2204 - if (cfg->has_lane_rst) 2205 - reset_control_assert(qphy->lane_rst); 2206 2368 2207 2369 return ret; 2208 2370 } ··· 2212 2380 clk_disable_unprepare(qphy->pipe_clk); 2213 2381 2214 2382 /* PHY reset */ 2215 - if (!cfg->no_pcs_sw_reset) 2216 - qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2383 + qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2217 2384 2218 2385 /* stop SerDes and Phy-Coding-Sublayer */ 2219 2386 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); ··· 2232 2401 static int qcom_qmp_phy_usb_exit(struct phy *phy) 2233 2402 { 2234 2403 struct qmp_phy *qphy = phy_get_drvdata(phy); 2235 - const struct qmp_phy_cfg *cfg = qphy->cfg; 2236 - 2237 - if (cfg->has_lane_rst) 2238 - reset_control_assert(qphy->lane_rst); 2239 2404 2240 2405 qcom_qmp_phy_usb_com_exit(qphy); 2241 2406 ··· 2503 2676 .owner = THIS_MODULE, 2504 2677 }; 2505 2678 2506 - static void qcom_qmp_reset_control_put(void *data) 2507 - { 2508 - reset_control_put(data); 2509 - } 2510 - 2511 2679 static 2512 2680 int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id, 2513 2681 void __iomem *serdes, const struct qmp_phy_cfg *cfg) ··· 2582 2760 "failed to get lane%d pipe_clk, %d\n", 2583 2761 id, ret); 2584 2762 return ret; 2585 - } 2586 - 2587 - /* Get lane reset, if any */ 2588 - if (cfg->has_lane_rst) { 2589 - snprintf(prop_name, sizeof(prop_name), "lane%d", id); 2590 - qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name); 2591 - if (IS_ERR(qphy->lane_rst)) { 2592 - dev_err(dev, "failed to get lane%d reset\n", id); 2593 - return PTR_ERR(qphy->lane_rst); 2594 - } 2595 - ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put, 2596 - qphy->lane_rst); 2597 - if (ret) 2598 - return ret; 2599 2763 } 2600 2764 2601 2765 generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);

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