Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-arm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC code updates from Arnd Bergmann:
"There are two notable changes this time:
- add a arch/arm/Kconfig.platforms file to simplify the platforms
that have no code except their Kconfig file (Andrew Davis)
- remove support for the ARM11MPCore CPU in the versatile/realview
platform. Since this is the last remaining one after removing
ox820, some core code can go as well (Linus Walleij)
The other changes are minor cleanups and bugfixes"
* tag 'soc-arm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: davinci: always select CONFIG_CPU_ARM926T
soc: pxa: ssp: fix casts
ARM: debug: fix DEBUG_UNCOMPRESS help for !MULTIPLATFORM
ARM: MAINTAINERS: drop empty entries for removed boards
ARM: Delete ARM11MPCore perf leftovers
ARM: mach-nspire: Rework support and directory structure
ARM: mach-sunplus: Rework support and directory structure
ARM: mach-airoha: Rework support and directory structure
ARM: mach-moxart: Move MOXA ART support into Kconfig.platforms
ARM: mach-uniphier: Move Socionext UniPhier support into Kconfig.platforms
ARM: mach-rda: Move RDA Micro support into Kconfig.platforms
ARM: mach-asm9260: Move ASM9260 support into Kconfig.platforms
ARM: Kconfig: move platform selection into its own Kconfig file
ARM: Delete ARM11MPCore (ARM11 ARMv6K SMP) support
MAINTAINERS: add Marvell MBus driver to Marvell EBU SoCs support
ARM: mxs: Do not search for "fsl,clkctrl"
ARM: imx: Use device_get_match_data()
MAINTAINERS: add omap bus drivers to OMAP2+ SUPPORT
ARM: at91: pm: set soc_pm.data.mode in at91_pm_secure_init()
+206
-498
+2
-22
MAINTAINERS
+2
-22
MAINTAINERS
···
2015
2015
S: Odd Fixes
2016
2016
N: clps711x
2017
2017
2018
-
ARM/CIRRUS LOGIC EDB9315A MACHINE SUPPORT
2019
-
M: Lennert Buytenhek <kernel@wantstofly.org>
2020
-
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2021
-
S: Maintained
2022
-
2023
2018
ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
2024
2019
M: Hartley Sweeten <hsweeten@visionengravers.com>
2025
2020
M: Alexander Sverdlin <alexander.sverdlin@gmail.com>
···
2300
2305
F: arch/arm/mach-mv78xx0/
2301
2306
F: arch/arm/mach-orion5x/
2302
2307
F: arch/arm/plat-orion/
2308
+
F: drivers/bus/mvebu-mbus.c
2303
2309
F: drivers/soc/dove/
2304
2310
2305
2311
ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
···
2817
2821
F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
2818
2822
F: arch/arm/boot/dts/sunplus/
2819
2823
F: arch/arm/configs/sp7021_*defconfig
2820
-
F: arch/arm/mach-sunplus/
2821
2824
F: drivers/clk/clk-sp7021.c
2822
2825
F: drivers/irqchip/irq-sp7021-intc.c
2823
2826
F: drivers/reset/reset-sunplus.c
···
2831
2836
F: arch/arm/boot/dts/synaptics/
2832
2837
F: arch/arm/mach-berlin/
2833
2838
F: arch/arm64/boot/dts/synaptics/
2834
-
2835
-
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
2836
-
M: Lennert Buytenhek <kernel@wantstofly.org>
2837
-
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2838
-
S: Maintained
2839
2839
2840
2840
ARM/TEGRA HDMI CEC SUBSYSTEM SUPPORT
2841
2841
M: Hans Verkuil <hverkuil-cisco@xs4all.nl>
···
2847
2857
L: linux-samsung-soc@vger.kernel.org
2848
2858
S: Maintained
2849
2859
F: arch/arm64/boot/dts/tesla/
2850
-
2851
-
ARM/TETON BGA MACHINE SUPPORT
2852
-
M: "Mark F. Brown" <mark.brown314@gmail.com>
2853
-
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2854
-
S: Maintained
2855
2860
2856
2861
ARM/TEXAS INSTRUMENT AEMIF/EMIF DRIVERS
2857
2862
M: Santosh Shilimkar <ssantosh@kernel.org>
···
2926
2941
F: Documentation/devicetree/bindings/soc/socionext/socionext,uniphier*.yaml
2927
2942
F: arch/arm/boot/dts/socionext/uniphier*
2928
2943
F: arch/arm/include/asm/hardware/cache-uniphier.h
2929
-
F: arch/arm/mach-uniphier/
2930
2944
F: arch/arm/mm/cache-uniphier.c
2931
2945
F: arch/arm64/boot/dts/socionext/uniphier*
2932
2946
F: drivers/bus/uniphier-system-bus.c
···
15858
15874
F: Documentation/devicetree/bindings/arm/ti/omap.yaml
15859
15875
F: arch/arm/configs/omap2plus_defconfig
15860
15876
F: arch/arm/mach-omap2/
15877
+
F: drivers/bus/omap*.[ch]
15861
15878
F: drivers/bus/ti-sysc.c
15862
15879
F: drivers/gpio/gpio-tps65219.c
15863
15880
F: drivers/i2c/busses/i2c-omap.c
···
19823
19838
F: Documentation/devicetree/bindings/display/simple-framebuffer.yaml
19824
19839
F: drivers/video/fbdev/simplefb.c
19825
19840
F: include/linux/platform_data/simplefb.h
19826
-
19827
-
SIMTEC EB110ATX (Chalice CATS)
19828
-
M: Simtec Linux Team <linux@simtec.co.uk>
19829
-
S: Supported
19830
-
W: http://www.simtec.co.uk/products/EB110ATX/
19831
19841
19832
19842
SIOX
19833
19843
M: Thorsten Scherer <t.scherer@eckelmann.de>
+1
-89
arch/arm/Kconfig
+1
-89
arch/arm/Kconfig
···
340
340
Selecting N here allows using those options, including
341
341
DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
342
342
343
-
menu "Platform selection"
344
-
depends on MMU
345
-
346
-
comment "CPU Core family selection"
347
-
348
-
config ARCH_MULTI_V4
349
-
bool "ARMv4 based platforms (FA526, StrongARM)"
350
-
depends on !ARCH_MULTI_V6_V7
351
-
# https://github.com/llvm/llvm-project/issues/50764
352
-
depends on !LD_IS_LLD || LLD_VERSION >= 160000
353
-
select ARCH_MULTI_V4_V5
354
-
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
355
-
356
-
config ARCH_MULTI_V4T
357
-
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
358
-
depends on !ARCH_MULTI_V6_V7
359
-
# https://github.com/llvm/llvm-project/issues/50764
360
-
depends on !LD_IS_LLD || LLD_VERSION >= 160000
361
-
select ARCH_MULTI_V4_V5
362
-
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
363
-
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
364
-
CPU_ARM925T || CPU_ARM940T)
365
-
366
-
config ARCH_MULTI_V5
367
-
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
368
-
depends on !ARCH_MULTI_V6_V7
369
-
select ARCH_MULTI_V4_V5
370
-
select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
371
-
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
372
-
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
373
-
374
-
config ARCH_MULTI_V4_V5
375
-
bool
376
-
377
-
config ARCH_MULTI_V6
378
-
bool "ARMv6 based platforms (ARM11)"
379
-
select ARCH_MULTI_V6_V7
380
-
select CPU_V6K
381
-
382
-
config ARCH_MULTI_V7
383
-
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
384
-
default y
385
-
select ARCH_MULTI_V6_V7
386
-
select CPU_V7
387
-
select HAVE_SMP
388
-
389
-
config ARCH_MULTI_V6_V7
390
-
bool
391
-
select MIGHT_HAVE_CACHE_L2X0
392
-
393
-
config ARCH_MULTI_CPU_AUTO
394
-
def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
395
-
select ARCH_MULTI_V5
396
-
397
-
endmenu
398
-
399
-
config ARCH_VIRT
400
-
bool "Dummy Virtual Machine"
401
-
depends on ARCH_MULTI_V7
402
-
select ARM_AMBA
403
-
select ARM_GIC
404
-
select ARM_GIC_V2M if PCI
405
-
select ARM_GIC_V3
406
-
select ARM_GIC_V3_ITS if PCI
407
-
select ARM_PSCI
408
-
select HAVE_ARM_ARCH_TIMER
409
-
410
-
config ARCH_AIROHA
411
-
bool "Airoha SoC Support"
412
-
depends on ARCH_MULTI_V7
413
-
select ARM_AMBA
414
-
select ARM_GIC
415
-
select ARM_GIC_V3
416
-
select ARM_PSCI
417
-
select HAVE_ARM_ARCH_TIMER
418
-
help
419
-
Support for Airoha EN7523 SoCs
343
+
source "arch/arm/Kconfig.platforms"
420
344
421
345
#
422
346
# This is sorted alphabetically by mach-* pathname. However, plat-*
···
352
428
source "arch/arm/mach-alpine/Kconfig"
353
429
354
430
source "arch/arm/mach-artpec/Kconfig"
355
-
356
-
source "arch/arm/mach-asm9260/Kconfig"
357
431
358
432
source "arch/arm/mach-aspeed/Kconfig"
359
433
···
401
479
402
480
source "arch/arm/mach-mmp/Kconfig"
403
481
404
-
source "arch/arm/mach-moxart/Kconfig"
405
-
406
482
source "arch/arm/mach-mstar/Kconfig"
407
483
408
484
source "arch/arm/mach-mv78xx0/Kconfig"
···
413
493
414
494
source "arch/arm/mach-npcm/Kconfig"
415
495
416
-
source "arch/arm/mach-nspire/Kconfig"
417
-
418
496
source "arch/arm/mach-omap1/Kconfig"
419
497
420
498
source "arch/arm/mach-omap2/Kconfig"
···
422
504
source "arch/arm/mach-pxa/Kconfig"
423
505
424
506
source "arch/arm/mach-qcom/Kconfig"
425
-
426
-
source "arch/arm/mach-rda/Kconfig"
427
507
428
508
source "arch/arm/mach-realtek/Kconfig"
429
509
···
445
529
446
530
source "arch/arm/mach-stm32/Kconfig"
447
531
448
-
source "arch/arm/mach-sunplus/Kconfig"
449
-
450
532
source "arch/arm/mach-sunxi/Kconfig"
451
533
452
534
source "arch/arm/mach-tegra/Kconfig"
453
-
454
-
source "arch/arm/mach-uniphier/Kconfig"
455
535
456
536
source "arch/arm/mach-ux500/Kconfig"
457
537
+2
-9
arch/arm/Kconfig.debug
+2
-9
arch/arm/Kconfig.debug
···
1809
1809
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
1810
1810
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
1811
1811
help
1812
-
This option influences the normal decompressor output for
1813
-
multiplatform kernels. Normally, multiplatform kernels disable
1814
-
decompressor output because it is not possible to know where to
1815
-
send the decompressor output.
1816
-
1817
-
When this option is set, the selected DEBUG_LL output method
1818
-
will be re-used for normal decompressor output on multiplatform
1819
-
kernels.
1820
-
1812
+
Say Y here to enable debug output in the decompressor code, using
1813
+
the selected DEBUG_LL output method.
1821
1814
1822
1815
config UNCOMPRESS_INCLUDE
1823
1816
string
+183
arch/arm/Kconfig.platforms
+183
arch/arm/Kconfig.platforms
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
menu "Platform selection"
4
+
depends on MMU
5
+
6
+
comment "CPU Core family selection"
7
+
8
+
config ARCH_MULTI_V4
9
+
bool "ARMv4 based platforms (FA526, StrongARM)"
10
+
depends on !ARCH_MULTI_V6_V7
11
+
# https://github.com/llvm/llvm-project/issues/50764
12
+
depends on !LD_IS_LLD || LLD_VERSION >= 160000
13
+
select ARCH_MULTI_V4_V5
14
+
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
15
+
16
+
config ARCH_MULTI_V4T
17
+
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
18
+
depends on !ARCH_MULTI_V6_V7
19
+
# https://github.com/llvm/llvm-project/issues/50764
20
+
depends on !LD_IS_LLD || LLD_VERSION >= 160000
21
+
select ARCH_MULTI_V4_V5
22
+
select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
23
+
CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
24
+
CPU_ARM925T || CPU_ARM940T)
25
+
26
+
config ARCH_MULTI_V5
27
+
bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
28
+
depends on !ARCH_MULTI_V6_V7
29
+
select ARCH_MULTI_V4_V5
30
+
select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
31
+
CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
32
+
CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
33
+
34
+
config ARCH_MULTI_V4_V5
35
+
bool
36
+
37
+
config ARCH_MULTI_V6
38
+
bool "ARMv6 based platforms (ARM11)"
39
+
select ARCH_MULTI_V6_V7
40
+
select CPU_V6K
41
+
42
+
config ARCH_MULTI_V7
43
+
bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
44
+
default y
45
+
select ARCH_MULTI_V6_V7
46
+
select CPU_V7
47
+
select HAVE_SMP
48
+
49
+
config ARCH_MULTI_V6_V7
50
+
bool
51
+
select MIGHT_HAVE_CACHE_L2X0
52
+
53
+
config ARCH_MULTI_CPU_AUTO
54
+
def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
55
+
select ARCH_MULTI_V5
56
+
57
+
endmenu
58
+
59
+
config ARCH_VIRT
60
+
bool "Dummy Virtual Machine"
61
+
depends on ARCH_MULTI_V7
62
+
select ARM_AMBA
63
+
select ARM_GIC
64
+
select ARM_GIC_V2M if PCI
65
+
select ARM_GIC_V3
66
+
select ARM_GIC_V3_ITS if PCI
67
+
select ARM_PSCI
68
+
select HAVE_ARM_ARCH_TIMER
69
+
70
+
config ARCH_AIROHA
71
+
bool "Airoha SoC Support"
72
+
depends on ARCH_MULTI_V7
73
+
select ARM_AMBA
74
+
select ARM_GIC
75
+
select ARM_GIC_V3
76
+
select ARM_PSCI
77
+
select HAVE_ARM_ARCH_TIMER
78
+
help
79
+
Support for Airoha EN7523 SoCs
80
+
81
+
config MACH_ASM9260
82
+
bool "Alphascale ASM9260"
83
+
depends on ARCH_MULTI_V5
84
+
depends on CPU_LITTLE_ENDIAN
85
+
select CPU_ARM926T
86
+
select ASM9260_TIMER
87
+
help
88
+
Support for Alphascale ASM9260 based platform.
89
+
90
+
menuconfig ARCH_MOXART
91
+
bool "MOXA ART SoC"
92
+
depends on ARCH_MULTI_V4
93
+
depends on CPU_LITTLE_ENDIAN
94
+
select CPU_FA526
95
+
select ARM_DMA_MEM_BUFFERABLE
96
+
select FARADAY_FTINTC010
97
+
select FTTMR010_TIMER
98
+
select GPIOLIB
99
+
select PHYLIB if NETDEVICES
100
+
help
101
+
Say Y here if you want to run your kernel on hardware with a
102
+
MOXA ART SoC.
103
+
The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
104
+
192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
105
+
Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
106
+
107
+
if ARCH_MOXART
108
+
109
+
config MACH_UC7112LX
110
+
bool "MOXA UC-7112-LX"
111
+
depends on ARCH_MOXART
112
+
help
113
+
Say Y here if you intend to run this kernel on a MOXA
114
+
UC-7112-LX embedded computer.
115
+
116
+
endif
117
+
118
+
config ARCH_NSPIRE
119
+
bool "TI-NSPIRE based"
120
+
depends on ARCH_MULTI_V4T
121
+
depends on CPU_LITTLE_ENDIAN
122
+
select CPU_ARM926T
123
+
select GENERIC_IRQ_CHIP
124
+
select ARM_AMBA
125
+
select ARM_VIC
126
+
select ARM_TIMER_SP804
127
+
select NSPIRE_TIMER
128
+
select POWER_RESET
129
+
select POWER_RESET_SYSCON
130
+
help
131
+
This enables support for systems using the TI-NSPIRE CPU
132
+
133
+
config ARCH_RDA
134
+
bool "RDA Micro SoCs"
135
+
depends on ARCH_MULTI_V7
136
+
select RDA_INTC
137
+
select RDA_TIMER
138
+
help
139
+
This enables support for the RDA Micro 8810PL SoC family.
140
+
141
+
menuconfig ARCH_SUNPLUS
142
+
bool "Sunplus SoCs"
143
+
depends on ARCH_MULTI_V7
144
+
help
145
+
Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
146
+
such as the Banana Pi BPI-F2S development board (and derivatives).
147
+
(<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
148
+
(<https://tibbo.com/store/plus1.html>)
149
+
150
+
if ARCH_SUNPLUS
151
+
152
+
config SOC_SP7021
153
+
bool "Sunplus SP7021 SoC support"
154
+
default ARCH_SUNPLUS
155
+
select HAVE_ARM_ARCH_TIMER
156
+
select ARM_GIC
157
+
select ARM_PSCI
158
+
select PINCTRL
159
+
select PINCTRL_SPPCTL
160
+
select SERIAL_SUNPLUS if TTY
161
+
select SERIAL_SUNPLUS_CONSOLE if TTY
162
+
help
163
+
Support for Sunplus SP7021 SoC. It is based on ARM 4-core
164
+
Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
165
+
Ethernet, etc.), FPGA interface, chip-to-chip bus.
166
+
It is designed for industrial control.
167
+
168
+
endif
169
+
170
+
config ARCH_UNIPHIER
171
+
bool "Socionext UniPhier SoCs"
172
+
depends on ARCH_MULTI_V7
173
+
select ARCH_HAS_RESET_CONTROLLER
174
+
select ARM_AMBA
175
+
select ARM_GLOBAL_TIMER
176
+
select ARM_GIC
177
+
select HAVE_ARM_SCU
178
+
select HAVE_ARM_TWD if SMP
179
+
select PINCTRL
180
+
select RESET_CONTROLLER
181
+
help
182
+
Support for UniPhier SoC family developed by Socionext Inc.
183
+
(formerly, System LSI Business Division of Panasonic Corporation)
-4
arch/arm/Makefile
-4
arch/arm/Makefile
···
167
167
# Machine directory name. This list is sorted alphanumerically
168
168
# by CONFIG_* macro name.
169
169
machine-$(CONFIG_ARCH_ACTIONS) += actions
170
-
machine-$(CONFIG_ARCH_AIROHA) += airoha
171
170
machine-$(CONFIG_ARCH_ALPINE) += alpine
172
171
machine-$(CONFIG_ARCH_ARTPEC) += artpec
173
172
machine-$(CONFIG_ARCH_ASPEED) += aspeed
···
191
192
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
192
193
machine-$(CONFIG_ARCH_MESON) += meson
193
194
machine-$(CONFIG_ARCH_MMP) += mmp
194
-
machine-$(CONFIG_ARCH_MOXART) += moxart
195
195
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
196
196
machine-$(CONFIG_ARCH_MVEBU) += mvebu
197
197
machine-$(CONFIG_ARCH_MXC) += imx
···
200
202
machine-$(CONFIG_ARCH_MSTARV7) += mstar
201
203
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
202
204
machine-$(CONFIG_ARCH_NPCM) += npcm
203
-
machine-$(CONFIG_ARCH_NSPIRE) += nspire
204
205
machine-$(CONFIG_ARCH_OMAP1) += omap1
205
206
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
206
207
machine-$(CONFIG_ARCH_ORION5X) += orion5x
···
215
218
machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
216
219
machine-$(CONFIG_ARCH_STI) += sti
217
220
machine-$(CONFIG_ARCH_STM32) += stm32
218
-
machine-$(CONFIG_ARCH_SUNPLUS) += sunplus
219
221
machine-$(CONFIG_ARCH_SUNXI) += sunxi
220
222
machine-$(CONFIG_ARCH_TEGRA) += tegra
221
223
machine-$(CONFIG_ARCH_U8500) += ux500
-124
arch/arm/kernel/perf_event_v6.c
-124
arch/arm/kernel/perf_event_v6.c
···
113
113
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
114
114
};
115
115
116
-
enum armv6mpcore_perf_types {
117
-
ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
118
-
ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
119
-
ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
120
-
ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
121
-
ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
122
-
ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
123
-
ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
124
-
ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
125
-
ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
126
-
ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
127
-
ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
128
-
ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
129
-
ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
130
-
ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
131
-
ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
132
-
ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
133
-
ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
134
-
ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
135
-
ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
136
-
ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
137
-
};
138
-
139
-
/*
140
-
* The hardware events that we support. We do support cache operations but
141
-
* we have harvard caches and no way to combine instruction and data
142
-
* accesses/misses in hardware.
143
-
*/
144
-
static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
145
-
PERF_MAP_ALL_UNSUPPORTED,
146
-
[PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
147
-
[PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
148
-
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
149
-
[PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
150
-
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
151
-
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
152
-
};
153
-
154
-
static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
155
-
[PERF_COUNT_HW_CACHE_OP_MAX]
156
-
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
157
-
PERF_CACHE_MAP_ALL_UNSUPPORTED,
158
-
159
-
[C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
160
-
[C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
161
-
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
162
-
[C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
163
-
164
-
[C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
165
-
166
-
/*
167
-
* The ARM performance counters can count micro DTLB misses, micro ITLB
168
-
* misses and main TLB misses. There isn't an event for TLB misses, so
169
-
* use the micro misses here and if users want the main TLB misses they
170
-
* can use a raw counter.
171
-
*/
172
-
[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
173
-
[C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
174
-
175
-
[C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
176
-
[C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
177
-
};
178
-
179
116
static inline unsigned long
180
117
armv6_pmcr_read(void)
181
118
{
···
375
438
armv6_pmcr_write(val);
376
439
}
377
440
378
-
static void armv6mpcore_pmu_disable_event(struct perf_event *event)
379
-
{
380
-
unsigned long val, mask, evt = 0;
381
-
struct hw_perf_event *hwc = &event->hw;
382
-
int idx = hwc->idx;
383
-
384
-
if (ARMV6_CYCLE_COUNTER == idx) {
385
-
mask = ARMV6_PMCR_CCOUNT_IEN;
386
-
} else if (ARMV6_COUNTER0 == idx) {
387
-
mask = ARMV6_PMCR_COUNT0_IEN;
388
-
} else if (ARMV6_COUNTER1 == idx) {
389
-
mask = ARMV6_PMCR_COUNT1_IEN;
390
-
} else {
391
-
WARN_ONCE(1, "invalid counter number (%d)\n", idx);
392
-
return;
393
-
}
394
-
395
-
/*
396
-
* Unlike UP ARMv6, we don't have a way of stopping the counters. We
397
-
* simply disable the interrupt reporting.
398
-
*/
399
-
val = armv6_pmcr_read();
400
-
val &= ~mask;
401
-
val |= evt;
402
-
armv6_pmcr_write(val);
403
-
}
404
-
405
441
static int armv6_map_event(struct perf_event *event)
406
442
{
407
443
return armpmu_map_event(event, &armv6_perf_map,
···
417
507
return 0;
418
508
}
419
509
420
-
/*
421
-
* ARMv6mpcore is almost identical to single core ARMv6 with the exception
422
-
* that some of the events have different enumerations and that there is no
423
-
* *hack* to stop the programmable counters. To stop the counters we simply
424
-
* disable the interrupt reporting and update the event. When unthrottling we
425
-
* reset the period and enable the interrupt reporting.
426
-
*/
427
-
428
-
static int armv6mpcore_map_event(struct perf_event *event)
429
-
{
430
-
return armpmu_map_event(event, &armv6mpcore_perf_map,
431
-
&armv6mpcore_perf_cache_map, 0xFF);
432
-
}
433
-
434
-
static int armv6mpcore_pmu_init(struct arm_pmu *cpu_pmu)
435
-
{
436
-
cpu_pmu->name = "armv6_11mpcore";
437
-
cpu_pmu->handle_irq = armv6pmu_handle_irq;
438
-
cpu_pmu->enable = armv6pmu_enable_event;
439
-
cpu_pmu->disable = armv6mpcore_pmu_disable_event;
440
-
cpu_pmu->read_counter = armv6pmu_read_counter;
441
-
cpu_pmu->write_counter = armv6pmu_write_counter;
442
-
cpu_pmu->get_event_idx = armv6pmu_get_event_idx;
443
-
cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx;
444
-
cpu_pmu->start = armv6pmu_start;
445
-
cpu_pmu->stop = armv6pmu_stop;
446
-
cpu_pmu->map_event = armv6mpcore_map_event;
447
-
cpu_pmu->num_events = 3;
448
-
449
-
return 0;
450
-
}
451
-
452
510
static const struct of_device_id armv6_pmu_of_device_ids[] = {
453
-
{.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
454
511
{.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init},
455
512
{.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init},
456
513
{ /* sentinel value */ }
···
427
550
ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init),
428
551
ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init),
429
552
ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init),
430
-
ARM_PMU_PROBE(ARM_CPU_PART_ARM11MPCORE, armv6mpcore_pmu_init),
431
553
{ /* sentinel value */ }
432
554
};
433
555
-2
arch/arm/mach-airoha/Makefile
-2
arch/arm/mach-airoha/Makefile
-16
arch/arm/mach-airoha/airoha.c
-16
arch/arm/mach-airoha/airoha.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Device Tree support for Airoha SoCs
4
-
*
5
-
* Copyright (c) 2022 Felix Fietkau <nbd@nbd.name>
6
-
*/
7
-
#include <asm/mach/arch.h>
8
-
9
-
static const char * const airoha_board_dt_compat[] = {
10
-
"airoha,en7523",
11
-
NULL,
12
-
};
13
-
14
-
DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)")
15
-
.dt_compat = airoha_board_dt_compat,
16
-
MACHINE_END
-9
arch/arm/mach-asm9260/Kconfig
-9
arch/arm/mach-asm9260/Kconfig
+3
arch/arm/mach-at91/pm.c
+3
arch/arm/mach-at91/pm.c
···
1103
1103
if (res.a0 == 0) {
1104
1104
pr_info("AT91: Secure PM: suspend mode set to %s\n",
1105
1105
pm_modes[suspend_mode].pattern);
1106
+
soc_pm.data.mode = suspend_mode;
1106
1107
return;
1107
1108
}
1108
1109
···
1113
1112
res = sam_smccc_call(SAMA5_SMC_SIP_GET_SUSPEND_MODE, 0, 0);
1114
1113
if (res.a0 == 0) {
1115
1114
pr_warn("AT91: Secure PM: failed to get default mode\n");
1115
+
soc_pm.data.mode = -1;
1116
1116
return;
1117
1117
}
1118
1118
···
1121
1119
pm_modes[suspend_mode].pattern);
1122
1120
1123
1121
soc_pm.data.suspend_mode = res.a1;
1122
+
soc_pm.data.mode = soc_pm.data.suspend_mode;
1124
1123
}
1125
1124
static const struct of_device_id atmel_shdwc_ids[] = {
1126
1125
{ .compatible = "atmel,sama5d2-shdwc" },
+1
arch/arm/mach-davinci/Kconfig
+1
arch/arm/mach-davinci/Kconfig
+4
-5
arch/arm/mach-imx/mmdc.c
+4
-5
arch/arm/mach-imx/mmdc.c
···
13
13
#include <linux/module.h>
14
14
#include <linux/of.h>
15
15
#include <linux/of_address.h>
16
-
#include <linux/of_device.h>
16
+
#include <linux/platform_device.h>
17
+
#include <linux/property.h>
17
18
#include <linux/perf_event.h>
18
19
#include <linux/slab.h>
19
20
···
104
103
struct device *dev;
105
104
struct perf_event *mmdc_events[MMDC_NUM_COUNTERS];
106
105
struct hlist_node node;
107
-
struct fsl_mmdc_devtype_data *devtype_data;
106
+
const struct fsl_mmdc_devtype_data *devtype_data;
108
107
struct clk *mmdc_ipg_clk;
109
108
};
110
109
···
475
474
struct mmdc_pmu *pmu_mmdc;
476
475
char *name;
477
476
int ret;
478
-
const struct of_device_id *of_id =
479
-
of_match_device(imx_mmdc_dt_ids, &pdev->dev);
480
477
481
478
pmu_mmdc = kzalloc(sizeof(*pmu_mmdc), GFP_KERNEL);
482
479
if (!pmu_mmdc) {
···
506
507
}
507
508
508
509
pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk;
509
-
pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data;
510
+
pmu_mmdc->devtype_data = device_get_match_data(&pdev->dev);
510
511
511
512
hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC,
512
513
HRTIMER_MODE_REL);
-28
arch/arm/mach-moxart/Kconfig
-28
arch/arm/mach-moxart/Kconfig
···
1
-
# SPDX-License-Identifier: GPL-2.0-only
2
-
menuconfig ARCH_MOXART
3
-
bool "MOXA ART SoC"
4
-
depends on ARCH_MULTI_V4
5
-
depends on CPU_LITTLE_ENDIAN
6
-
select CPU_FA526
7
-
select ARM_DMA_MEM_BUFFERABLE
8
-
select FARADAY_FTINTC010
9
-
select FTTMR010_TIMER
10
-
select GPIOLIB
11
-
select PHYLIB if NETDEVICES
12
-
help
13
-
Say Y here if you want to run your kernel on hardware with a
14
-
MOXA ART SoC.
15
-
The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
16
-
192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
17
-
Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
18
-
19
-
if ARCH_MOXART
20
-
21
-
config MACH_UC7112LX
22
-
bool "MOXA UC-7112-LX"
23
-
depends on ARCH_MOXART
24
-
help
25
-
Say Y here if you intend to run this kernel on a MOXA
26
-
UC-7112-LX embedded computer.
27
-
28
-
endif
-4
arch/arm/mach-moxart/Makefile
-4
arch/arm/mach-moxart/Makefile
-6
arch/arm/mach-moxart/moxart.c
-6
arch/arm/mach-moxart/moxart.c
+3
-1
arch/arm/mach-mxs/mach-mxs.c
+3
-1
arch/arm/mach-mxs/mach-mxs.c
···
356
356
{
357
357
struct device_node *np;
358
358
359
-
np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
359
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
360
+
if (!np)
361
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
360
362
reset_addr = of_iomap(np, 0);
361
363
if (!reset_addr)
362
364
return -ENODEV;
-15
arch/arm/mach-nspire/Kconfig
-15
arch/arm/mach-nspire/Kconfig
···
1
-
# SPDX-License-Identifier: GPL-2.0-only
2
-
config ARCH_NSPIRE
3
-
bool "TI-NSPIRE based"
4
-
depends on ARCH_MULTI_V4T
5
-
depends on CPU_LITTLE_ENDIAN
6
-
select CPU_ARM926T
7
-
select GENERIC_IRQ_CHIP
8
-
select ARM_AMBA
9
-
select ARM_VIC
10
-
select ARM_TIMER_SP804
11
-
select NSPIRE_TIMER
12
-
select POWER_RESET
13
-
select POWER_RESET_SYSCON
14
-
help
15
-
This enables support for systems using the TI-NSPIRE CPU
-2
arch/arm/mach-nspire/Makefile
-2
arch/arm/mach-nspire/Makefile
-18
arch/arm/mach-nspire/nspire.c
-18
arch/arm/mach-nspire/nspire.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
4
-
*/
5
-
6
-
#include <asm/mach/arch.h>
7
-
8
-
static const char *const nspire_dt_match[] __initconst = {
9
-
"ti,nspire",
10
-
"ti,nspire-cx",
11
-
"ti,nspire-tp",
12
-
"ti,nspire-clp",
13
-
NULL,
14
-
};
15
-
16
-
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
17
-
.dt_compat = nspire_dt_match,
18
-
MACHINE_END
-8
arch/arm/mach-rda/Kconfig
-8
arch/arm/mach-rda/Kconfig
-27
arch/arm/mach-sunplus/Kconfig
-27
arch/arm/mach-sunplus/Kconfig
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
3
-
menuconfig ARCH_SUNPLUS
4
-
bool "Sunplus SoCs"
5
-
depends on ARCH_MULTI_V7
6
-
help
7
-
Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
8
-
such as the Banana Pi BPI-F2S development board (and derivatives).
9
-
(<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
10
-
(<https://tibbo.com/store/plus1.html>)
11
-
12
-
config SOC_SP7021
13
-
bool "Sunplus SP7021 SoC support"
14
-
depends on ARCH_SUNPLUS
15
-
default ARCH_SUNPLUS
16
-
select HAVE_ARM_ARCH_TIMER
17
-
select ARM_GIC
18
-
select ARM_PSCI
19
-
select PINCTRL
20
-
select PINCTRL_SPPCTL
21
-
select SERIAL_SUNPLUS if TTY
22
-
select SERIAL_SUNPLUS_CONSOLE if TTY
23
-
help
24
-
Support for Sunplus SP7021 SoC. It is based on ARM 4-core
25
-
Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
26
-
Ethernet, etc.), FPGA interface, chip-to-chip bus.
27
-
It is designed for industrial control.
-8
arch/arm/mach-sunplus/Makefile
-8
arch/arm/mach-sunplus/Makefile
-16
arch/arm/mach-sunplus/sp7021.c
-16
arch/arm/mach-sunplus/sp7021.c
···
1
-
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
/*
3
-
* Copyright (C) Sunplus Technology Co., Ltd.
4
-
* All rights reserved.
5
-
*/
6
-
#include <linux/kernel.h>
7
-
#include <asm/mach/arch.h>
8
-
9
-
static const char *sp7021_compat[] __initconst = {
10
-
"sunplus,sp7021",
11
-
NULL
12
-
};
13
-
14
-
DT_MACHINE_START(SP7021_DT, "SP7021")
15
-
.dt_compat = sp7021_compat,
16
-
MACHINE_END
-15
arch/arm/mach-uniphier/Kconfig
-15
arch/arm/mach-uniphier/Kconfig
···
1
-
# SPDX-License-Identifier: GPL-2.0
2
-
config ARCH_UNIPHIER
3
-
bool "Socionext UniPhier SoCs"
4
-
depends on ARCH_MULTI_V7
5
-
select ARCH_HAS_RESET_CONTROLLER
6
-
select ARM_AMBA
7
-
select ARM_GLOBAL_TIMER
8
-
select ARM_GIC
9
-
select HAVE_ARM_SCU
10
-
select HAVE_ARM_TWD if SMP
11
-
select PINCTRL
12
-
select RESET_CONTROLLER
13
-
help
14
-
Support for UniPhier SoC family developed by Socionext Inc.
15
-
(formerly, System LSI Business Division of Panasonic Corporation)
-17
arch/arm/mach-versatile/Kconfig
-17
arch/arm/mach-versatile/Kconfig
···
201
201
Enable support for the Cortex-A9MPCore tile fitted to the
202
202
Realview(R) Emulation Baseboard platform.
203
203
204
-
config REALVIEW_EB_ARM11MP
205
-
bool "Support ARM11MPCore Tile"
206
-
depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
207
-
select HAVE_SMP
208
-
help
209
-
Enable support for the ARM11MPCore tile fitted to the Realview(R)
210
-
Emulation Baseboard platform.
211
-
212
-
config MACH_REALVIEW_PB11MP
213
-
bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
214
-
depends on ARCH_MULTI_V6
215
-
select HAVE_SMP
216
-
help
217
-
Include support for the ARM(R) RealView(R) Platform Baseboard for
218
-
the ARM11MPCore. This platform has an on-board ARM11MPCore and has
219
-
support for PCI-E and Compact Flash.
220
-
221
204
# ARMv6 CPU without K extensions, but does have the new exclusive ops
222
205
config MACH_REALVIEW_PB1176
223
206
bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
+5
-1
arch/arm/mach-versatile/platsmp-realview.c
+5
-1
arch/arm/mach-versatile/platsmp-realview.c
···
18
18
#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
19
19
20
20
static const struct of_device_id realview_scu_match[] = {
21
+
/*
22
+
* The ARM11MP SCU compatible is only provided as fallback for
23
+
* old RealView EB Cortex-A9 device trees that were using this
24
+
* compatible by mistake.
25
+
*/
21
26
{ .compatible = "arm,arm11mp-scu", },
22
27
{ .compatible = "arm,cortex-a9-scu", },
23
28
{ .compatible = "arm,cortex-a5-scu", },
···
32
27
static const struct of_device_id realview_syscon_match[] = {
33
28
{ .compatible = "arm,core-module-integrator", },
34
29
{ .compatible = "arm,realview-eb-syscon", },
35
-
{ .compatible = "arm,realview-pb11mp-syscon", },
36
30
{ .compatible = "arm,realview-pbx-syscon", },
37
31
{ },
38
32
};
-1
arch/arm/mach-versatile/realview.c
-1
arch/arm/mach-versatile/realview.c
-18
arch/arm/mm/Kconfig
-18
arch/arm/mm/Kconfig
···
937
937
You must have glibc 2.22 or later for programs to seamlessly
938
938
take advantage of this.
939
939
940
-
config DMA_CACHE_RWFO
941
-
bool "Enable read/write for ownership DMA cache maintenance"
942
-
depends on CPU_V6K && SMP
943
-
default y
944
-
help
945
-
The Snoop Control Unit on ARM11MPCore does not detect the
946
-
cache maintenance operations and the dma_{map,unmap}_area()
947
-
functions may leave stale cache entries on other CPUs. By
948
-
enabling this option, Read or Write For Ownership in the ARMv6
949
-
DMA cache maintenance functions is performed. These LDR/STR
950
-
instructions change the cache line state to shared or modified
951
-
so that the cache operation has the desired effect.
952
-
953
-
Note that the workaround is only valid on processors that do
954
-
not perform speculative loads into the D-cache. For such
955
-
processors, if cache maintenance operations are not broadcast
956
-
in hardware, other workarounds are needed (e.g. cache
957
-
maintenance broadcasting in software via FIQ).
958
940
959
941
config OUTER_CACHE
960
942
bool
-31
arch/arm/mm/cache-v6.S
-31
arch/arm/mm/cache-v6.S
···
201
201
* - end - virtual end address of region
202
202
*/
203
203
v6_dma_inv_range:
204
-
#ifdef CONFIG_DMA_CACHE_RWFO
205
-
ldrb r2, [r0] @ read for ownership
206
-
strb r2, [r0] @ write for ownership
207
-
#endif
208
204
tst r0, #D_CACHE_LINE_SIZE - 1
209
205
bic r0, r0, #D_CACHE_LINE_SIZE - 1
210
206
#ifdef HARVARD_CACHE
···
209
213
mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
210
214
#endif
211
215
tst r1, #D_CACHE_LINE_SIZE - 1
212
-
#ifdef CONFIG_DMA_CACHE_RWFO
213
-
ldrbne r2, [r1, #-1] @ read for ownership
214
-
strbne r2, [r1, #-1] @ write for ownership
215
-
#endif
216
216
bic r1, r1, #D_CACHE_LINE_SIZE - 1
217
217
#ifdef HARVARD_CACHE
218
218
mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
···
223
231
#endif
224
232
add r0, r0, #D_CACHE_LINE_SIZE
225
233
cmp r0, r1
226
-
#ifdef CONFIG_DMA_CACHE_RWFO
227
-
ldrlo r2, [r0] @ read for ownership
228
-
strlo r2, [r0] @ write for ownership
229
-
#endif
230
234
blo 1b
231
235
mov r0, #0
232
236
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
···
236
248
v6_dma_clean_range:
237
249
bic r0, r0, #D_CACHE_LINE_SIZE - 1
238
250
1:
239
-
#ifdef CONFIG_DMA_CACHE_RWFO
240
-
ldr r2, [r0] @ read for ownership
241
-
#endif
242
251
#ifdef HARVARD_CACHE
243
252
mcr p15, 0, r0, c7, c10, 1 @ clean D line
244
253
#else
···
254
269
* - end - virtual end address of region
255
270
*/
256
271
ENTRY(v6_dma_flush_range)
257
-
#ifdef CONFIG_DMA_CACHE_RWFO
258
-
ldrb r2, [r0] @ read for ownership
259
-
strb r2, [r0] @ write for ownership
260
-
#endif
261
272
bic r0, r0, #D_CACHE_LINE_SIZE - 1
262
273
1:
263
274
#ifdef HARVARD_CACHE
···
263
282
#endif
264
283
add r0, r0, #D_CACHE_LINE_SIZE
265
284
cmp r0, r1
266
-
#ifdef CONFIG_DMA_CACHE_RWFO
267
-
ldrblo r2, [r0] @ read for ownership
268
-
strblo r2, [r0] @ write for ownership
269
-
#endif
270
285
blo 1b
271
286
mov r0, #0
272
287
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
···
278
301
add r1, r1, r0
279
302
teq r2, #DMA_FROM_DEVICE
280
303
beq v6_dma_inv_range
281
-
#ifndef CONFIG_DMA_CACHE_RWFO
282
304
b v6_dma_clean_range
283
-
#else
284
-
teq r2, #DMA_TO_DEVICE
285
-
beq v6_dma_clean_range
286
-
b v6_dma_flush_range
287
-
#endif
288
305
ENDPROC(v6_dma_map_area)
289
306
290
307
/*
···
288
317
* - dir - DMA direction
289
318
*/
290
319
ENTRY(v6_dma_unmap_area)
291
-
#ifndef CONFIG_DMA_CACHE_RWFO
292
320
add r1, r1, r0
293
321
teq r2, #DMA_TO_DEVICE
294
322
bne v6_dma_inv_range
295
-
#endif
296
323
ret lr
297
324
ENDPROC(v6_dma_unmap_area)
298
325
+2
-2
drivers/soc/pxa/ssp.c
+2
-2
drivers/soc/pxa/ssp.c
···
152
152
if (dev->of_node) {
153
153
const struct of_device_id *id =
154
154
of_match_device(of_match_ptr(pxa_ssp_of_ids), dev);
155
-
ssp->type = (int) id->data;
155
+
ssp->type = (uintptr_t) id->data;
156
156
} else {
157
157
const struct platform_device_id *id =
158
158
platform_get_device_id(pdev);
159
-
ssp->type = (int) id->driver_data;
159
+
ssp->type = id->driver_data;
160
160
161
161
/* PXA2xx/3xx SSP ports starts from 1 and the internal pdev->id
162
162
* starts from 0, do a translation here