tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dmaengine: idxd: Add Max SGL Size Support for DSA3.0

Certain DSA 3.0 opcodes, such as Gather copy and Gather reduce, require max
SGL configured for workqueues prior to supporting these opcodes.

Configure the maximum scatter-gather list (SGL) size for workqueues during
setup on the supported HW. Application can then properly handle the SGL
size without explicitly setting it.

Signed-off-by: Yi Sun <yi.sun@intel.com>
Co-developed-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Link: https://patch.msgid.link/20260107-idxd-yi-sun-dsa3-sgl-size-v2-2-dbef8f559e48@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Yi Sun and committed by
Vinod Koul fe7b87d9 8308510b

+28 -1
+5
drivers/dma/idxd/device.c
··· 390 390 memset(wq->name, 0, WQ_NAME_SIZE); 391 391 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 392 392 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 393 + idxd_wq_set_init_max_sgl_size(idxd, wq); 393 394 if (wq->opcap_bmap) 394 395 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 395 396 } ··· 990 989 /* bytes 12-15 */ 991 990 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 992 991 idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size)); 992 + if (idxd_sgl_supported(idxd)) 993 + wq->wqcfg->max_sgl_shift = ilog2(wq->max_sgl_size); 993 994 994 995 /* bytes 32-63 */ 995 996 if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) { ··· 1170 1167 1171 1168 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1172 1169 idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift); 1170 + if (idxd_sgl_supported(idxd)) 1171 + wq->max_sgl_size = 1U << wq->wqcfg->max_sgl_shift; 1173 1172 1174 1173 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1175 1174 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
+16
drivers/dma/idxd/idxd.h
··· 227 227 char name[WQ_NAME_SIZE + 1]; 228 228 u64 max_xfer_bytes; 229 229 u32 max_batch_size; 230 + u32 max_sgl_size; 230 231 231 232 /* Lock to protect upasid_xa access. */ 232 233 struct mutex uc_lock; ··· 349 348 350 349 u64 max_xfer_bytes; 351 350 u32 max_batch_size; 351 + u32 max_sgl_size; 352 352 int max_groups; 353 353 int max_engines; 354 354 int max_rdbufs; ··· 692 690 wq->max_batch_size = 0; 693 691 else 694 692 wq->max_batch_size = max_batch_size; 693 + } 694 + 695 + static bool idxd_sgl_supported(struct idxd_device *idxd) 696 + { 697 + return idxd->data->type == IDXD_TYPE_DSA && 698 + idxd->hw.version >= DEVICE_VERSION_3 && 699 + idxd->hw.dsacap0.sgl_formats; 700 + } 701 + 702 + static inline void idxd_wq_set_init_max_sgl_size(struct idxd_device *idxd, 703 + struct idxd_wq *wq) 704 + { 705 + if (idxd_sgl_supported(idxd)) 706 + wq->max_sgl_size = 1U << idxd->hw.dsacap0.max_sgl_shift; 695 707 } 696 708 697 709 static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg,
+5
drivers/dma/idxd/init.c
··· 222 222 init_completion(&wq->wq_resurrect); 223 223 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 224 224 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 225 + idxd_wq_set_init_max_sgl_size(idxd, wq); 225 226 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 226 227 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 227 228 if (!wq->wqcfg) { ··· 590 589 idxd->hw.dsacap0.bits = ioread64(idxd->reg_base + IDXD_DSACAP0_OFFSET); 591 590 idxd->hw.dsacap1.bits = ioread64(idxd->reg_base + IDXD_DSACAP1_OFFSET); 592 591 idxd->hw.dsacap2.bits = ioread64(idxd->reg_base + IDXD_DSACAP2_OFFSET); 592 + } 593 + if (idxd_sgl_supported(idxd)) { 594 + idxd->max_sgl_size = 1U << idxd->hw.dsacap0.max_sgl_shift; 595 + dev_dbg(dev, "max sgl size: %u\n", idxd->max_sgl_size); 593 596 } 594 597 595 598 /* read iaa cap */
+2 -1
drivers/dma/idxd/registers.h
··· 390 390 /* bytes 12-15 */ 391 391 u32 max_xfer_shift:5; 392 392 u32 max_batch_shift:4; 393 - u32 rsvd4:23; 393 + u32 max_sgl_shift:4; 394 + u32 rsvd4:19; 394 395 395 396 /* bytes 16-19 */ 396 397 u16 occupancy_inth;