Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
echoplayer: drive LCD parallel bus using STM32 LTDC
This is much, much faster than using SPI and is able to
offload the CPU completely.
Change-Id: Ia4c0289775296fe41d594ba849bd057e8482306e
authored by
Aidan MacDonald
and committed by
Solomon Peachy
4ceb9e22
e98dc793
+172
-38
+1
firmware/target/arm/stm32/clock-stm32h7.h
+1
firmware/target/arm/stm32/clock-stm32h7.h
+38
-6
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
+38
-6
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
···
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*
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****************************************************************************/
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#include "clock-stm32h7.h"
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#include "lcd-echoplayer.h"
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#include "panic.h"
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#include "regs/stm32h743/flash.h"
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#include "regs/stm32h743/fmc.h"
···
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static void init_pll(void)
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{
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-
/* Select HSE/4 input for PLL1 (6 MHz) */
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/* For simplicity, PLL parameters are hardcoded */
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_Static_assert(STM32_HSE_FREQ == 24000000,
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"HSE frequency not correct");
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_Static_assert(LCD_DOTCLOCK_FREQ == 6199200,
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"PLL3 parameters not correct for dot clock");
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+
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/*
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* Use HSE/4 input for PLL1
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* Use HSE/16 input for PLL3
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*/
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reg_writef(RCC_PLLCKSELR,
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PLLSRC_V(HSE),
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DIVM1(4),
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DIVM2(0),
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DIVM3(0));
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DIVM3(16));
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/* Enable PLL1P and PLL1Q */
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/* Enable PLL1P, PLL1Q, PLL3R */
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reg_writef(RCC_PLLCFGR,
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DIVP1EN(1),
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DIVQ1EN(1),
···
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DIVR2EN(0),
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DIVP3EN(0),
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DIVQ3EN(0),
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-
DIVR3EN(0),
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DIVR3EN(1),
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PLL1RGE_V(4_8MHZ),
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-
PLL1VCOSEL_V(WIDE));
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PLL1VCOSEL_V(WIDE),
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PLL1FRACEN(0),
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PLL3RGE_V(1_2MHZ),
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PLL3VCOSEL_V(MEDIUM),
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PLL3FRACEN(0));
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reg_writef(RCC_PLL1DIVR,
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DIVN(80 - 1), /* 6 * 80 = 480 MHz */
···
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DIVQ(8 - 1), /* 480 / 8 = 60 MHz */
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DIVR(1 - 1));
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reg_writef(RCC_CR, PLL1ON(1));
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reg_writef(RCC_PLL3FRACR, FRACN(1468));
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reg_writef(RCC_PLL3DIVR,
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DIVN(161 - 1), /* approx 241.768 MHz */
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DIVP(1 - 1),
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DIVQ(1 - 1),
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DIVR(39 - 1)); /* approx 6.1992 MHz */
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reg_writef(RCC_PLLCFGR, PLL3FRACEN(1));
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reg_writef(RCC_CR, PLL1ON(1), PLL3ON(1));
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while (!reg_readf(RCC_CR, PLL1RDY));
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while (!reg_readf(RCC_CR, PLL3RDY));
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}
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static void init_vos(void)
···
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static void init_periph_clock(void)
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{
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reg_writef(RCC_D2CCIP1R, SPI45SEL_V(HSE));
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/* Enable AXI SRAM in sleep mode to allow DMA'ing out of it */
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reg_writef(RCC_AHB3LPENR, AXISRAMEN(1));
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}
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void stm_target_clock_init(void)
···
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case STM_CLOCK_SPI5_KER:
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reg_writef(RCC_APB2ENR, SPI5EN(enable));
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reg_writef(RCC_APB2LPENR, SPI5EN(enable));
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break;
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case STM_CLOCK_LTDC_KER:
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reg_writef(RCC_APB3ENR, LTDCEN(enable));
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reg_writef(RCC_APB3LPENR, LTDCEN(enable));
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break;
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default:
+71
-32
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.c
+71
-32
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.c
···
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#include "system.h"
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#include "kernel.h"
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#include "lcd.h"
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#include "lcd-echoplayer.h"
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#include "nvic-arm.h"
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#include "spi-stm32h7.h"
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#include "gpio-stm32h7.h"
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#include "clock-stm32h7.h"
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#include "regs/stm32h743/rcc.h"
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#include "regs/stm32h743/spi.h"
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#include "regs/stm32h743/ltdc.h"
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/* ILI9342C specifies 10 MHz max */
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#define LCD_SPI_FREQ 10000000
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/*
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* ILI9342C specifies 10 MHz max
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*
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* Use 12MHz for now -- for some reason using 6 MHz doesn't work
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* to enable RGB mode, but works fine to send graphics in SPI mode?
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*/
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#define LCD_SPI_FREQ 12000000
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struct stm_spi_config spi_cfg = {
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.instance = ITA_SPI5,
···
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stm_spi_transmit(&spi, arr, sizeof(arr)); \
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} while (0)
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-
static void set_row_column_address(int x, int y, int w, int h)
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static void init_ltdc(void)
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{
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ili_cmd(0x2a, x >> 8, x & 0xff, (w-1) >> 8, (w-1) & 0xff);
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ili_cmd(0x2b, y >> 8, y & 0xff, (h-1) >> 8, (h-1) & 0xff);
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/* Enable LTDC clock */
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stm_clock_enable(STM_CLOCK_LTDC_KER);
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/* Set timing parameters */
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const uint32_t hsw = LCD_HSW - 1;
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const uint32_t ahbp = hsw + LCD_HBP;
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const uint32_t aaw = ahbp + LCD_HAW;
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const uint32_t totw = aaw + LCD_HFP;
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const uint32_t vsh = LCD_VSH - 1;
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const uint32_t avbp = vsh + LCD_VBP;
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const uint32_t aah = avbp + LCD_VAH;
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const uint32_t toth = aah + LCD_VFP;
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+
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reg_writef(LTDC_SSCR, HSW(hsw), VSH(vsh));
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reg_writef(LTDC_BPCR, AHBP(ahbp), AVBP(avbp));
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reg_writef(LTDC_AWCR, AAW(aaw), AAH(aah));
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reg_writef(LTDC_TWCR, TOTALW(totw), TOTALH(toth));
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/* Set interface polarity */
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reg_writef(LTDC_GCR, HSPOL(0), VSPOL(0), DEPOL(0), PCPOL(0), DEN(0));
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/* Enable layer 1 to blit framebuffer to whole screen */
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const uint32_t row_bytes = LCD_WIDTH * FB_DATA_SZ;
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reg_assignf(LTDC_LAYER_WHPCR(0), WHSPPOS(ahbp + LCD_HAW), WHSTPOS(ahbp + 1));
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reg_assignf(LTDC_LAYER_WVPCR(0), WVSPPOS(avbp + LCD_VAH), WVSTPOS(avbp + 1));
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reg_assignf(LTDC_LAYER_PFCR(0), PF(BV_LTDC_LAYER_PFCR_PF_RGB565));
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reg_var(LTDC_LAYER_CFBAR(0)) = (uintptr_t)FBADDR(0, 0);
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reg_assignf(LTDC_LAYER_CFBLR(0), CFBP(row_bytes), CFBLL(row_bytes + 7));
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reg_assignf(LTDC_LAYER_CFBLNR(0), CFBLNBR(LCD_HEIGHT));
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reg_assignf(LTDC_LAYER_CR(0), LEN(1));
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/* Reload shadow registers to enable layer 1 */
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reg_writef(LTDC_SRCR, IMR(1));
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/* Enable LTDC output */
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reg_writef(LTDC_GCR, LTDCEN(1));
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}
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void lcd_init_device(void)
···
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/* Configure SPI bus */
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stm_spi_init(&spi, &spi_cfg);
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nvic_enable_irq(NVIC_IRQN_SPI5);
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/* Enable LCD controller */
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init_ltdc();
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/* Ensure controller is reset */
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gpio_set_level(GPIO_LCD_RESET, 0);
···
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/* memory access control (X/Y invert, BGR panel) */
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ili_cmd(0x36, 0xc8);
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/* pixel format set (16bpp) */
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ili_cmd(0x3a, 0x55);
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/* pixel format set (18bpp for RGB bus, 16bpp for SPI bus) */
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ili_cmd(0x3a, 0x65);
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/* send set EXTC command to allow configuring RGB interface */
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ili_cmd(0xc8, 0xff, 0x93, 0x42);
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/*
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* Enable RGB interface transferring to internal GRAM.
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*
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* Direct to shift register mode doesn't work; for one, the
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* framebuffer doesn't get transferred properly which might
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* just be timing issues. Two, the display is horizontally
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* flipped and there doesn't seem to be a way to change it
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* in the shift register mode.
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*/
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ili_cmd(0xb0, 0xc0);
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ili_cmd(0xf6, 0x01, 0x00, 0x06);
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/* display ON */
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ili_cmd(0x29);
···
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void lcd_update(void)
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{
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lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
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commit_dcache();
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}
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void lcd_update_rect(int x, int y, int width, int height)
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{
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/* row buffer to minimize time wasted in post-transaction delay */
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static uint16_t row[LCD_WIDTH * 2];
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-
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if (x < 0)
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x = 0;
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else if (x >= LCD_WIDTH)
···
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if (height > LCD_HEIGHT - y)
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height = LCD_HEIGHT - y;
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set_row_column_address(x, y, width, height);
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ili_cmd(0x2c);
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for (int py = y; py < height; ++py)
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{
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for (int px = x; px < width; ++px)
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{
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fb_data *fb = FBADDR(px, py);
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uint16_t *data = &row[px * 2];
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-
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data[0] = 0x100;
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data[0] |= (FB_UNPACK_RED(*fb) >> 3) << 3;
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data[0] |= (FB_UNPACK_GREEN(*fb) >> 5);
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-
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data[1] = 0x100;
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data[1] |= ((FB_UNPACK_GREEN(*fb) >> 2) & 0x7) << 5;
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data[1] |= (FB_UNPACK_BLUE(*fb) >> 3);
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}
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stm_spi_transmit(&spi, &row[x * 2], width * sizeof(*row) * 2);
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}
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for (int dy = y; dy < height; ++dy)
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commit_dcache_range(FBADDR(x, dy), FB_DATA_SZ * width);
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}
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void spi5_irq_handler(void)
+62
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.h
+62
firmware/target/arm/stm32/echoplayer/lcd-echoplayer.h
···
1
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __LCD_ECHOPLAYER_H__
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#define __LCD_ECHOPLAYER_H__
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+
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#include "config.h"
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+
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/* Hsync pulse width in units of dot clocks */
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#define LCD_HSW 10
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+
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/* Hsync back porch in units of dot clocks */
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#define LCD_HBP 20
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/* Horizontal active width in units of dot clocks */
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#define LCD_HAW LCD_WIDTH
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+
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/* Hsync front porch in units of dot clocks */
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#define LCD_HFP 10
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+
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/* Vsync pulse height in units of horizontal lines */
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#define LCD_VSH 2
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+
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/* Vsync back porch in units of horizontal lines */
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#define LCD_VBP 2
43
+
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/* Vertical active height in units of horizontal lines */
45
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#define LCD_VAH LCD_HEIGHT
46
+
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/* Vsync front porch in units of horizontal lines */
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#define LCD_VFP 2
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+
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/* Total horizontal width in dots */
51
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#define LCD_HWIDTH (LCD_HSW + LCD_HBP + LCD_HAW + LCD_HFP)
52
+
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/* Total vertical height in lines */
54
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#define LCD_VHEIGHT (LCD_VSH + LCD_VBP + LCD_VAH + LCD_VFP)
55
+
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/* Target frame rate */
57
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#define LCD_FPS 70
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+
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/* Dot clock frequency */
60
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#define LCD_DOTCLOCK_FREQ (LCD_FPS * LCD_HWIDTH * LCD_VHEIGHT)
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#endif /* __LCD_ECHOPLAYER_H__ */