Rockbox open source high quality audio player as a Music Player Daemon
mpris
rockbox
mpd
libadwaita
audio
rust
zig
deno
S5L8702: Move I/O addresses and bit masks from clocking driver to SoC definitions, reuse existing definitions
No difference in the produced binaries for ipod6g (normal and bootloader)
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Change-Id: Ib79c5539a317aae350d661ab23c181471ee38abb
+187
-194
+187
-11
firmware/export/s5l87xx.h
+187
-11
firmware/export/s5l87xx.h
···
170
170
#define CLKCON3 (*((REG32_PTR_T)(CLK_BASE + 0x0C)))
171
171
#define CLKCON4 (*((REG32_PTR_T)(CLK_BASE + 0x10)))
172
172
#define CLKCON5 (*((REG32_PTR_T)(CLK_BASE + 0x14)))
173
-
#define PLL0PMS (*((REG32_PTR_T)(CLK_BASE + 0x20)))
174
-
#define PLL1PMS (*((REG32_PTR_T)(CLK_BASE + 0x24)))
175
-
#define PLL2PMS (*((REG32_PTR_T)(CLK_BASE + 0x28)))
176
-
#define PLL0LCNT (*((REG32_PTR_T)(CLK_BASE + 0x30)))
177
-
#define PLL1LCNT (*((REG32_PTR_T)(CLK_BASE + 0x34)))
178
-
#define PLL2LCNT (*((REG32_PTR_T)(CLK_BASE + 0x38)))
173
+
174
+
#define CLKCON0_SDR_DISABLE_BIT (1 << 31)
175
+
#if CONFIG_CPU == S5L8720
176
+
#define CLKCON0_UNK30_BIT (1 << 30)
177
+
#endif
178
+
179
+
/* CPU/AHB/APB real_divisor =
180
+
xDIV_EN_BIT ? 2*(reg_value+1) : 1 */
181
+
#define CLKCON1_CDIV_POS 24
182
+
#define CLKCON1_CDIV_MSK 0x1f
183
+
#define CLKCON1_CDIV_EN_BIT (1 << 30)
184
+
185
+
#define CLKCON1_HDIV_POS 16
186
+
#define CLKCON1_HDIV_MSK 0x1f
187
+
#define CLKCON1_HDIV_EN_BIT (1 << 22)
188
+
189
+
#define CLKCON1_PDIV_POS 8
190
+
#define CLKCON1_PDIV_MSK 0x1f
191
+
#define CLKCON1_PDIV_EN_BIT (1 << 14)
192
+
193
+
/* AHB/APB ratio: must be written when HDIV and/or PDIV
194
+
are modified, real_ratio = reg_value + 1 */
195
+
#define CLKCON1_HPRAT_POS 0
196
+
#define CLKCON1_HPRAT_MSK 0x3f
197
+
198
+
/* TBC: this bit selects a clock routed (at least) to all I2S modules
199
+
* (AUDAUX_Clk, see i2s-s5l8702.h), it can be selected as a source
200
+
* for CODEC_CLK (MCLK), on iPod Classic AUDAUX_Clk is:
201
+
* 0 -> 12 MHz (TBC: OSC0 ???)
202
+
* 1 -> 24 MHz (TBC: 2*OSC0 ???)
203
+
*/
204
+
#define CLKCON5_AUDAUXCLK_BIT (1 << 31)
205
+
206
+
#define PLLPMS(i) (*((REG32_PTR_T)(CLK_BASE + 0x20 + ((i) * 4))))
207
+
#define PLL0PMS PLLPMS(0)
208
+
#define PLL1PMS PLLPMS(1)
209
+
#define PLL2PMS PLLPMS(2)
210
+
211
+
/*
212
+
* PLLnPMS
213
+
*/
214
+
#define PLLPMS_PDIV_POS 24 /* pre-divider */
215
+
#define PLLPMS_PDIV_MSK 0x3f
216
+
#define PLLPMS_MDIV_POS 8 /* main divider */
217
+
#define PLLPMS_MDIV_MSK 0xff
218
+
#define PLLPMS_SDIV_POS 0 /* post-divider (2^S) */
219
+
#define PLLPMS_SDIV_MSK 0x7
220
+
221
+
#define PLLCNT(i) (*((REG32_PTR_T)(CLK_BASE + 0x30 + ((i) * 4))))
222
+
#define PLLCNT_MSK 0x3fffff
223
+
#define PLL0LCNT PLLCNT(0)
224
+
#define PLL1LCNT PLLCNT(1)
225
+
#define PLL2LCNT PLLCNT(2)
226
+
#if CONFIG_CPU == S5L8720
227
+
#define PLLUNK3C (*((REG32_PTR_T)(CLK_BASE + 0x3C)))
228
+
#endif
179
229
#define PLLLOCK (*((REG32_PTR_T)(CLK_BASE + 0x40)))
230
+
231
+
/* Start status:
232
+
0 -> in progress, 1 -> locked */
233
+
#define PLLLOCK_LCK_BIT(n) (1 << (n))
234
+
235
+
/* Lock status for Divisor Mode (DM):
236
+
0 -> DM unlocked, 1 -> DM locked */
237
+
#define PLLLOCK_DMLCK_BIT(n) (1 << (4 + (n)))
238
+
180
239
#define PLLMODE (*((REG32_PTR_T)(CLK_BASE + 0x44)))
240
+
241
+
/* Enable PLL0,1,2:
242
+
0 -> turned off, 1 -> turned on */
243
+
#define PLLMODE_EN_BIT(n) (1 << (n))
244
+
245
+
/* Select PMS mode for PLL0,1:
246
+
0 -> mutiply mode (MM), 1 -> divide mode (DM) */
247
+
#define PLLMODE_PMSMOD_BIT(n) (1 << (4 + (n)))
248
+
249
+
/* Select DMOSC for PLL2:
250
+
0 -> DMOSC_STD, 1 -> DMOSC_ALT */
251
+
#define PLLMODE_PLL2DMOSC_BIT (1 << 6)
252
+
253
+
/* Select oscilator for CG16_SEL_OSC source:
254
+
0 -> S5L8702_OSC0, 1 -> S5L8702_OSC1 */
255
+
#define PLLMODE_OSCSEL_BIT (1 << 8)
256
+
257
+
/* Select PLLxClk (a.k.a. "slow mode", see s3c2440-DS) for PLL0,1,2:
258
+
O -> S5L8702_OSC1, 1 -> PLLxFreq */
259
+
#define PLLMODE_PLLOUT_BIT(n) (1 << (16 + (n)))
260
+
181
261
/* s5l8702 only uses PWRCON0 and PWRCON1 */
182
262
#define PWRCON(i) (*((REG32_PTR_T)(CLK_BASE \
183
263
+ ((i) == 4 ? 0x6C : \
···
185
265
((i) == 2 ? 0x58 : \
186
266
((i) == 1 ? 0x4C : \
187
267
0x48)))))))
268
+
269
+
/* TBC: ATM i am assuming that PWRCON_AHB/APB registers are clockgates
270
+
* for SoC internal controllers sitting on AHB/APB buses, this is based
271
+
* on other similar SoC documentation and experimental results for many
272
+
* (not all) s5l8702 controllers.
273
+
*/
274
+
#define PWRCON_AHB PWRCON(0)
275
+
#define PWRCON_APB PWRCON(1)
276
+
188
277
/* SW Reset Control Register */
189
278
#define SWRCON (*((REG32_PTR_T)(CLK_BASE + 0x50)))
190
279
/* Reset Status Register */
···
193
282
#define RSTSR_SWR_BIT (1 << 1)
194
283
#define RSTSR_HWR_BIT (1 << 0)
195
284
196
-
#if CONFIG_CPU==S5L8720
197
-
#define CLKCON6 (*((volatile uint32_t*)(CLK_BASE + 0x70)))
198
-
#endif
199
-
#endif
285
+
#if CONFIG_CPU == S5L8702
286
+
#define PLLMOD2 (*((REG32_PTR_T)(CLK_BASE + 0x60)))
287
+
288
+
/* Selects ALTOSCx for PLL0,1,2 when DMOSC == DMOSC_ALT:
289
+
0 -> S5L8702_ALTOSC0, 1 -> S5L8702_ALTOSC1 */
290
+
#define PLLMOD2_ALTOSC_BIT(n) (1 << (n))
291
+
292
+
/* Selects DMOSC for PLL0,1:
293
+
0 -> DMOSC_STD, 1 -> DMOSC_ALT */
294
+
#define PLLMOD2_DMOSC_BIT(n) (1 << (4 + (n)))
295
+
296
+
#elif CONFIG_CPU==S5L8720
297
+
#define PLLUNK64 (*((REG32_PTR_T)(CLK_BASE + 0x64))) // used by efi_ClockAndReset
298
+
#define CLKCON6 (*((REG32_PTR_T)(CLK_BASE + 0x70)))
299
+
#endif /* CONFIG_CPU==S5L8720 */
300
+
#endif /* CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720 */
301
+
302
+
200
303
201
304
#if CONFIG_CPU==S5L8700
202
305
#define CLOCKGATE_UARTC 8
···
341
444
#define CLOCKGATE_TIMERD_2 151
342
445
#endif
343
446
447
+
#if CONFIG_CPU == S5L8702 || CONFIG_CPU == S5L8720
448
+
/* CG16_x: for readability and debug, these gates are defined as
449
+
* 16-bit registers, on HW they are really halves of 32-bit registers.
450
+
* Some functionallity is not available on all CG16 gates (when so,
451
+
* related bits are read-only and fixed to 0).
452
+
*
453
+
* CLKCONx DIV1 DIV2 UNKOSC UNK14
454
+
* CG16_SYS 0L +
455
+
* CG16_2L 2L + +(TBC) +(TBC)
456
+
* CG16_SVID 2H + +(TBC)
457
+
* CG16_AUD0 3L + +
458
+
* CG16_AUD1 3H + +
459
+
* CG16_AUD2 4L + +
460
+
* CG16_RTIME 4H + + +
461
+
* CG16_5L 5L +
462
+
*
463
+
* Not all gates are fully tested, this information is mainly based
464
+
* on experimental test using emCORE:
465
+
* - CG16_SYS and CG16_RTIME were tested mainly using time benchs.
466
+
* - EClk is used as a fixed clock (not depending on CPU/AHB/APB
467
+
* settings) for the timer controller. MIU_Clk is used by the MIU
468
+
* controller to generate the DRAM refresh signals.
469
+
* - AUDxClk are a source selection for I2Sx modules, so they can
470
+
* can be scaled and routed to the I2S GPIO ports, where they
471
+
* were sampled (using emCORE) to inspect how they behave.
472
+
* - CG16_SVID seem to be used for external video, this info is
473
+
* based on OF diagnostics reverse engineering.
474
+
* - CG16_2L and CG16_5L usage is unknown.
475
+
*/
476
+
#define CG16_SYS (*((REG16_PTR_T)(CLK_BASE)))
477
+
#if CONFIG_CPU == S5L8702
478
+
#define CG16_2L (*((REG16_PTR_T)(CLK_BASE + 0x08)))
479
+
#elif CONFIG_CPU == S5L8720
480
+
#define CG16_LCD (*((REG16_PTR_T)(CLK_BASE + 0x08)))
481
+
#endif
482
+
#define CG16_SVID (*((REG16_PTR_T)(CLK_BASE + 0x0A)))
483
+
#define CG16_AUD0 (*((REG16_PTR_T)(CLK_BASE + 0x0C)))
484
+
#define CG16_AUD1 (*((REG16_PTR_T)(CLK_BASE + 0x0E)))
485
+
#define CG16_AUD2 (*((REG16_PTR_T)(CLK_BASE + 0x10)))
486
+
#define CG16_RTIME (*((REG16_PTR_T)(CLK_BASE + 0x12)))
487
+
#define CG16_5L (*((REG16_PTR_T)(CLK_BASE + 0x14)))
488
+
#if CONFIG_CPU == S5L8720
489
+
#define CG16_6L (*((REG16_PTR_T)(CLK_BASE + 0x70)))
490
+
#endif
491
+
492
+
/* CG16 output frequency =
493
+
!DISABLE_BIT * SEL_x frequency / DIV1+1 / DIV2+1 */
494
+
#define CG16_DISABLE_BIT (1 << 15) /* mask clock output */
495
+
#define CG16_UNK14_BIT (1 << 14) /* writable on CG16_2L */
496
+
497
+
#define CG16_SEL_POS 12 /* source clock selection */
498
+
#define CG16_SEL_MSK 0x3
499
+
#define CG16_SEL_OSC 0
500
+
#define CG16_SEL_PLL0 1
501
+
#define CG16_SEL_PLL1 2
502
+
#define CG16_SEL_PLL2 3
503
+
504
+
#define CG16_UNKOSC_BIT (1 << 11)
505
+
506
+
#define CG16_DIV2_POS 4 /* 2nd divisor */
507
+
#define CG16_DIV2_MSK 0xf
508
+
509
+
#define CG16_DIV1_POS 0 /* 1st divisor */
510
+
#define CG16_DIV1_MSK 0xf
511
+
512
+
/* SM1 */
513
+
#define SM1_BASE 0x38500000
514
+
515
+
/* TBC: Clk_SM1 = HClk / (SM1_DIV[3:0] + 1) */
516
+
#define SM1_DIV (*((REG32_PTR_T)(SM1_BASE + 0x1000)))
517
+
#endif
518
+
344
519
/* 06. INTERRUPT CONTROLLER UNIT */
345
520
#define INT_BASE 0x39C00000
346
521
···
423
598
#define MIUCOM (*(REG32_PTR_T)(MIU_BASE + 0x104)) /* Command and status register */
424
599
#define MIUMRS (*(REG32_PTR_T)(MIU_BASE + 0x110)) /* SDRAM Mode Register Set Value Register */
425
600
426
-
#define UNK3E000008 (*(REG32_PTR_T)(0x3e000008))
601
+
#define UNK3E000000_BASE 0x3e000000
602
+
#define UNK3E000008 (*(REG32_PTR_T)(UNK3E000000_BASE + 0x08))
427
603
#endif
428
604
429
605
/* DDR */
-183
firmware/target/arm/s5l8702/clocking-s5l8702.h
-183
firmware/target/arm/s5l8702/clocking-s5l8702.h
···
196
196
197
197
#include "s5l87xx.h"
198
198
199
-
/* TBC: ATM i am assuming that PWRCON_AHB/APB registers are clockgates
200
-
* for SoC internal controllers sitting on AHB/APB buses, this is based
201
-
* on other similar SoC documentation and experimental results for many
202
-
* (not all) s5l8702 controllers.
203
-
*/
204
-
#define PWRCON_AHB (*((uint32_t volatile*)(0x3C500048)))
205
-
#define PWRCON_APB (*((uint32_t volatile*)(0x3C50004c)))
206
-
207
-
#define PLLPMS(i) (*((volatile uint32_t*)(0x3C500020 + ((i) * 4))))
208
-
#define PLLCNT(i) (*((volatile uint32_t*)(0x3C500030 + ((i) * 4))))
209
-
#define PLLCNT_MSK 0x3fffff
210
-
#if CONFIG_CPU == S5L8702
211
-
#define PLLMOD2 (*((volatile uint32_t*)(0x3C500060)))
212
-
#elif CONFIG_CPU == S5L8720
213
-
#define PLLUNK3C (*((volatile uint32_t*)(0x3C50003C)))
214
-
#define PLLUNK64 (*((volatile uint32_t*)(0x3C500064))) // used by efi_ClockAndReset
215
-
#endif
216
-
217
-
/* TBC: Clk_SM1 = HClk / (SM1_DIV[3:0] + 1) */
218
-
#define SM1_DIV (*((volatile uint32_t*)(0x38501000)))
219
-
220
-
221
-
/* CG16_x: for readability and debug, these gates are defined as
222
-
* 16-bit registers, on HW they are really halves of 32-bit registers.
223
-
* Some functionallity is not available on all CG16 gates (when so,
224
-
* related bits are read-only and fixed to 0).
225
-
*
226
-
* CLKCONx DIV1 DIV2 UNKOSC UNK14
227
-
* CG16_SYS 0L +
228
-
* CG16_2L 2L + +(TBC) +(TBC)
229
-
* CG16_SVID 2H + +(TBC)
230
-
* CG16_AUD0 3L + +
231
-
* CG16_AUD1 3H + +
232
-
* CG16_AUD2 4L + +
233
-
* CG16_RTIME 4H + + +
234
-
* CG16_5L 5L +
235
-
*
236
-
* Not all gates are fully tested, this information is mainly based
237
-
* on experimental test using emCORE:
238
-
* - CG16_SYS and CG16_RTIME were tested mainly using time benchs.
239
-
* - EClk is used as a fixed clock (not depending on CPU/AHB/APB
240
-
* settings) for the timer controller. MIU_Clk is used by the MIU
241
-
* controller to generate the DRAM refresh signals.
242
-
* - AUDxClk are a source selection for I2Sx modules, so they can
243
-
* can be scaled and routed to the I2S GPIO ports, where they
244
-
* were sampled (using emCORE) to inspect how they behave.
245
-
* - CG16_SVID seem to be used for external video, this info is
246
-
* based on OF diagnostics reverse engineering.
247
-
* - CG16_2L and CG16_5L usage is unknown.
248
-
*/
249
-
#define CG16_SYS (*((volatile uint16_t*)(0x3C500000)))
250
-
#if CONFIG_CPU == S5L8702
251
-
#define CG16_2L (*((volatile uint16_t*)(0x3C500008)))
252
-
#elif CONFIG_CPU == S5L8720
253
-
#define CG16_LCD (*((volatile uint16_t*)(0x3C500008)))
254
-
#endif
255
-
#define CG16_SVID (*((volatile uint16_t*)(0x3C50000A)))
256
-
#define CG16_AUD0 (*((volatile uint16_t*)(0x3C50000C)))
257
-
#define CG16_AUD1 (*((volatile uint16_t*)(0x3C50000E)))
258
-
#define CG16_AUD2 (*((volatile uint16_t*)(0x3C500010)))
259
-
#define CG16_RTIME (*((volatile uint16_t*)(0x3C500012)))
260
-
#define CG16_5L (*((volatile uint16_t*)(0x3C500014)))
261
-
#if CONFIG_CPU == S5L8720
262
-
#define CG16_6L (*((volatile uint16_t*)(0x3C500070)))
263
-
#endif
264
-
265
-
/* CG16 output frequency =
266
-
!DISABLE_BIT * SEL_x frequency / DIV1+1 / DIV2+1 */
267
-
#define CG16_DISABLE_BIT (1 << 15) /* mask clock output */
268
-
#define CG16_UNK14_BIT (1 << 14) /* writable on CG16_2L */
269
-
270
-
#define CG16_SEL_POS 12 /* source clock selection */
271
-
#define CG16_SEL_MSK 0x3
272
-
#define CG16_SEL_OSC 0
273
-
#define CG16_SEL_PLL0 1
274
-
#define CG16_SEL_PLL1 2
275
-
#define CG16_SEL_PLL2 3
276
-
277
-
#define CG16_UNKOSC_BIT (1 << 11)
278
-
279
-
#define CG16_DIV2_POS 4 /* 2nd divisor */
280
-
#define CG16_DIV2_MSK 0xf
281
-
282
-
#define CG16_DIV1_POS 0 /* 1st divisor */
283
-
#define CG16_DIV1_MSK 0xf
284
-
285
-
/*
286
-
* CLKCON0
287
-
*/
288
-
#define CLKCON0_SDR_DISABLE_BIT (1 << 31)
289
-
#if CONFIG_CPU == S5L8720
290
-
#define CLKCON0_UNK30_BIT (1 << 30)
291
-
#endif
292
-
293
-
/*
294
-
* CLKCON1
295
-
*/
296
-
/* CPU/AHB/APB real_divisor =
297
-
xDIV_EN_BIT ? 2*(reg_value+1) : 1 */
298
-
#define CLKCON1_CDIV_POS 24
299
-
#define CLKCON1_CDIV_MSK 0x1f
300
-
#define CLKCON1_CDIV_EN_BIT (1 << 30)
301
-
302
-
#define CLKCON1_HDIV_POS 16
303
-
#define CLKCON1_HDIV_MSK 0x1f
304
-
#define CLKCON1_HDIV_EN_BIT (1 << 22)
305
-
306
-
#define CLKCON1_PDIV_POS 8
307
-
#define CLKCON1_PDIV_MSK 0x1f
308
-
#define CLKCON1_PDIV_EN_BIT (1 << 14)
309
-
310
-
/* AHB/APB ratio: must be written when HDIV and/or PDIV
311
-
are modified, real_ratio = reg_value + 1 */
312
-
#define CLKCON1_HPRAT_POS 0
313
-
#define CLKCON1_HPRAT_MSK 0x3f
314
-
315
-
/*
316
-
* CLKCON5
317
-
*/
318
-
/* TBC: this bit selects a clock routed (at least) to all I2S modules
319
-
* (AUDAUX_Clk, see i2s-s5l8702.h), it can be selected as a source
320
-
* for CODEC_CLK (MCLK), on iPod Classic AUDAUX_Clk is:
321
-
* 0 -> 12 MHz (TBC: OSC0 ???)
322
-
* 1 -> 24 MHz (TBC: 2*OSC0 ???)
323
-
*/
324
-
#define CLKCON5_AUDAUXCLK_BIT (1 << 31)
325
-
326
-
/*
327
-
* PLLnPMS
328
-
*/
329
-
#define PLLPMS_PDIV_POS 24 /* pre-divider */
330
-
#define PLLPMS_PDIV_MSK 0x3f
331
-
#define PLLPMS_MDIV_POS 8 /* main divider */
332
-
#define PLLPMS_MDIV_MSK 0xff
333
-
#define PLLPMS_SDIV_POS 0 /* post-divider (2^S) */
334
-
#define PLLPMS_SDIV_MSK 0x7
335
-
336
-
/*
337
-
* PLLLOCK
338
-
*/
339
-
/* Start status:
340
-
0 -> in progress, 1 -> locked */
341
-
#define PLLLOCK_LCK_BIT(n) (1 << (n))
342
-
343
-
/* Lock status for Divisor Mode (DM):
344
-
0 -> DM unlocked, 1 -> DM locked */
345
-
#define PLLLOCK_DMLCK_BIT(n) (1 << (4 + (n)))
346
-
347
-
/*
348
-
* PLLMODE
349
-
*/
350
-
/* Enable PLL0,1,2:
351
-
0 -> turned off, 1 -> turned on */
352
-
#define PLLMODE_EN_BIT(n) (1 << (n))
353
-
354
-
/* Select PMS mode for PLL0,1:
355
-
0 -> mutiply mode (MM), 1 -> divide mode (DM) */
356
-
#define PLLMODE_PMSMOD_BIT(n) (1 << (4 + (n)))
357
-
358
-
/* Select DMOSC for PLL2:
359
-
0 -> DMOSC_STD, 1 -> DMOSC_ALT */
360
-
#define PLLMODE_PLL2DMOSC_BIT (1 << 6)
361
-
362
-
/* Select oscilator for CG16_SEL_OSC source:
363
-
0 -> S5L8702_OSC0, 1 -> S5L8702_OSC1 */
364
-
#define PLLMODE_OSCSEL_BIT (1 << 8)
365
-
366
-
/* Select PLLxClk (a.k.a. "slow mode", see s3c2440-DS) for PLL0,1,2:
367
-
O -> S5L8702_OSC1, 1 -> PLLxFreq */
368
-
#define PLLMODE_PLLOUT_BIT(n) (1 << (16 + (n)))
369
-
370
-
/*
371
-
* PLLMOD2
372
-
*/
373
-
/* Selects ALTOSCx for PLL0,1,2 when DMOSC == DMOSC_ALT:
374
-
0 -> S5L8702_ALTOSC0, 1 -> S5L8702_ALTOSC1 */
375
-
#define PLLMOD2_ALTOSC_BIT(n) (1 << (n))
376
-
377
-
/* Selects DMOSC for PLL0,1:
378
-
0 -> DMOSC_STD, 1 -> DMOSC_ALT */
379
-
#define PLLMOD2_DMOSC_BIT(n) (1 << (4 + (n)))
380
-
381
-
382
199
/* See s3c2440-DS (figure 7.2) for similar SoC reference.
383
200
*
384
201
* There are two different PMS modes, PLLxFreq is: